ITC shines light on new Mentor Test announcements

ITC shines light on new Mentor Test announcements
by Tom Simon on 11-18-2019 at 10:00 am

The 50th International Test Conference was just held in Washington DC, where papers, sessions, workshops and announcements addressing the increasing complexity and expanding use of semiconductors showed that innovations in test are crucial to design and product success. Test methodologies and even the scope of test have … Read More


Reducing the Cost of SoC Testing

Reducing the Cost of SoC Testing
by Daniel Payne on 12-16-2016 at 12:00 pm

Every year certain technology themes appear, like at ITC this year a big theme was how to reduce the cost of SoC testing. I spoke with Rob Knoth of Cadence by phone to hear more about this cost of test theme. Rob gave me an example of an SoC that takes 27 seconds on a tester, so at $0.04 per second in test costs amounts to $1.08 per part. If you… Read More


DFT Approaches for Giga-gate SoC Designs

DFT Approaches for Giga-gate SoC Designs
by Daniel Payne on 10-26-2016 at 12:00 pm

In the early days of IC design there were arguments against using any extra transistors or gates for testability purposes, because that would be adding extra silicon area which in turn would drive up the costs of the chip and product. Today we are older and wiser, realizing that there are product pricing benefits to quickly test each… Read More


Three New Things from ITC this year

Three New Things from ITC this year
by Daniel Payne on 10-23-2015 at 12:00 pm

The NFL has its annual Super Bowl contest each year, EDA vendors attend DAC, then the test folks attend ITCwhich was in Anaheim a few weeks ago. I’ve marketed ATGP, BIST and DFT tools before so I like to keep updated on what’s happening at conferences like ITC. Robert Ruiz from Synopsys spoke with me by phone to provide … Read More


What’s next in test compression?

What’s next in test compression?
by Beth Martin on 10-10-2014 at 4:45 pm

If you’ll be at ITC TestWeek in Seattle (Oct 20-23), here’s one event you don’t want to miss: a technology reception hosted by Mentor, with Janusz Rajski and Nilanjan Mukherjee as the featured speakers. It is free to ITC attendees and you can register here. [If for some crazy reason you haven’t registered for ITC yet, do that… Read More


What Mentor Said at ITC

What Mentor Said at ITC
by Beth Martin on 09-26-2013 at 4:47 pm

At the ITC test conference in early September, Mentor made three announcements. ITC is a big event for Mentor’s test group, and where they usually roll out their new tools and capabilities. The indefatigable Steve Pateras was captured on film describing them.

I’ve summarize Mentor’s three announcements and added… Read More


Early Test –> Less Expensive, Better Health, Faster Closure

Early Test –> Less Expensive, Better Health, Faster Closure
by Pawan Fangaria on 09-18-2013 at 11:00 am


I am talking about the health of electronic and semiconductor design, which if made sound at RTL stage, can set it right for the rest of the design cycle for faster closure and also at lesser cost. Last week was the week of ITC(International Test Conference) for the Semiconductor and EDA community. I was looking forward to what ITCRead More


A Hybrid Test Approach – Combining ATPG and BIST

A Hybrid Test Approach – Combining ATPG and BIST
by Daniel Payne on 09-09-2013 at 5:18 pm

In the world of IC testability we tend to look at various approaches as independent means to an end, namely high test coverage with the minimum amount of test time, minimum area impact, minimum timing impact, and acceptable power use. Automatic Test Pattern Generation (ATPG) is a software-based approach that can be applied to any… Read More


SpyGlass: Focusing on Test

SpyGlass: Focusing on Test
by Paul McLellan on 09-07-2013 at 5:51 pm

For decades we have used a model of faults in chips that assumes that a given signal is stuck-at-0 or stuck-at-1. And when I say decades, I mean it. The D-algorithm was invented at IBM in 1966, the year after Gordon Moore made a now very famous observation about the number of transistors on an integrated circuit. We know that stuck-at… Read More


Test, The Forgotten Step-Child of Semiconductor Design

Test, The Forgotten Step-Child of Semiconductor Design
by Paul McLellan on 08-20-2013 at 7:56 pm

Somehow, when designing a chip it is synthesis and place & route that gets all the attention. But it is no good taping out perfect layout without also having away to test the silicon. Somehow, test just isn’t as glamorous.

On September 10-12th is the International Test Conference which, as usual, is at the Disneyland Hotel… Read More