Every year certain technology themes appear, like at ITC this year a big theme was how to reduce the cost of SoC testing. I spoke with Rob Knoth of Cadence by phone to hear more about this cost of test theme. Rob gave me an example of an SoC that takes 27 seconds on a tester, so at $0.04 per second in test costs amounts to $1.08 per part. If you multiply that $1.08 per part times millions of parts, then your test costs are in the millions, so any technology that can maintain high fault coverage and yet at the same time reduce the test time will produce savings in the millions of dollars. So the real challenge is how to achieve acceptable levels of fault coverage without growing the die size or making convergence difficult.
Earlier in 2016 the technologists at Cadence introduced a new way to do on-chip test compression as part of their new software offering called Modus. Traditional test compression techniques that use an XOR structure start to take up more silicon space as you crank up the compression ratio higher and higher. The Cadence compression and decompression approach is up to 3X more effective in reducing test times than older techniques offered. Just take a look at the comparison shown below of a traditional XOR compression on the left with the massive wiring congestions to the same design on the right using Modus 2D compression. I’ll pick the one one the right side any day because it is less congested and offers a higher compression ratio, meaning that I save in test times.
Modus 2D compression yields a 400X compression ratio
Related blog – Cadence Adds New Dimension to SoC Test Solution
In our EDA industry we often believe that new, disruptive technologies can only come from small, focused start-ups, however in this case we see an established vendor like Cadence take the time to rewrite their tools in order to meet new design and test challenges. Here’s how the Modus test tool fits into an overall digital design flow:
Cadence digital design flow
Compression hardware for improving test isn’t a new concept, the folks at IBM pioneered this concept many years ago and LogicVision was an early commercial vendor offering compression. Using logic synthesis (Genus) and DFT tools (Modus) from the same vendor ensures that there are no timing differences between design and test.
Related blog – Digital Design Trends, A Cadence Perspective
EDA and semiconductor IP vendors have taken notice of the growing automotive market and responded to the safety challenges that are required by the ISO 26262 standard. Two months ago it was announced that Cadence has Tool Confidence Level 1 (TCL1) documentation to meet the ISO 26262 standard, as determined by TÜV SÜD an accredited independent testing and conformity assessment company. Cadence users can further benefit by downloading the Automotive Functional Safety Kits where you get:
- Safety manual for the specific design flow
- Tool Confidence Analysis (TCA) documents for each tool in the chain
- Compliance report from TÜV SÜD
Cadence has a long history of working with automotive customers like TI, so they know how to save them valuable time in being compliant with the ISO standard. Beyond just focusing on tool-level compliance, you can use three Cadence flows that are compliant:
- Analog Mixed-Signal Design & Verification
- Digital Front-end Design & Verification
- Digital Implementation and Signoff
There are now over 30 Cadence tools predetermined for TCL1.
Related blog – Top Ten Insights on the EDA and Semiconductor Industry
You may have an old idea of what Cadence has to offer in DFT, ATPG, compression and BIST, so now is a good time to give Modus a closer look because it’s new technology that is up for the challenges of reducing the cost of SoC testing. If you’re working on large SoCs, with long test times and have high volumes, then it could really benefit your bottom line to reduce the test times using this newer technology.