Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)

Webinar: FPGA Design Verification in a Nutshell Part 1: Verification Planning (US)
by Admin on 08-07-2023 at 4:51 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)

Webinar: FPGA Design Verification in a Nutshell Part 3: Advanced Verification Methods (US)
by Admin on 08-07-2023 at 4:49 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)

Webinar: FPGA Design Verification in a Nutshell Part 2: Advanced Testbench Implementation (US)
by Admin on 08-07-2023 at 4:48 pm

Time: 11:00 AM – 12:00 PM (PDT)

Abstract

As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA testing and… Read More


Webinar: Athermal Lens System Design with Ansys Zemax OpticStudio

Webinar: Athermal Lens System Design with Ansys Zemax OpticStudio
by Admin on 07-24-2023 at 4:15 pm

Optical and optomechanical Systems must perform well not only in simulation but also in real-world conditions. For systems exposed to temperature changes, one of the key goals is to achieve athermalization, where the system has high performance across a range of operating temperatures.

Join Udit Kumar and Flurin Herren of Ansys… Read More


Webinar: Simulation-Driven Design Using Tapes & Adhesives

Webinar: Simulation-Driven Design Using Tapes & Adhesives
by Admin on 06-13-2023 at 4:00 pm

SimuTech Group presents exclusive 3M Webinar

Join us for an engaging and informative webinar on Simulation-Driven Design, where SimuTech Group and 3M engineers explore the cutting-edge advancements in the realm of tapes and adhesives.

Discover how these essential components are transforming the landscape of product development,

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Webinar: Embedding Sustainable Design in Teaching

Webinar: Embedding Sustainable Design in Teaching
by Admin on 06-13-2023 at 3:56 pm

Acquiring knowledge for the responsible production of goods is highly valued by both engineering students and industry. This webinar presents a case study on a sustainable product design methodology to help educators embed eco-design thinking in their student’s decision-making process in product development.

TIME:
JUNE

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Mastering MicroLED Design: A Multiphysics Approach

Mastering MicroLED Design: A Multiphysics Approach
by Admin on 06-13-2023 at 3:55 pm

Join us for an in-depth exploration of the Ansys Lumerical Suite of tools for optoelectronic and photonic simulations of MicroLED devices during this upcoming webinar.

Time:
June 20, 2023

Venue:
Virtual

About this Webinar

MicroLED technology is revolutionizing how we think about displays and lighting, offering promising

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Webinar: Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family

Webinar: Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
by Admin on 06-13-2023 at 3:07 pm

Wednesday, June 14, 2023 | 10:00 a.m. – 11:00 a.m. CEST

Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage

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