Rather than watch the World Cup battle for third place, my beautiful wife and I spent last Saturday afternoon at the CASPA Wearables Symposium. The most interesting presentation was from Samsung because it included slides on their foundry offering. In regards to wearables, I still don’t see the ROI I need to buy one, yet. We are getting… Read More
Tag: 16nm
Cliff Hou’s DAC Keynote
Cliff Hou had two major appearances at DAC this year. He gave the opening day keynote…and he wrote the forward to Dan and my bookFabless: the Transformation of the Semiconductor Industry which about 1500 lucky people got a copy of courtesy of several companies, most notably eSilicon who sponsored the Tuesday evening post-conference… Read More
Xilinx’s 16nm vs. Altera 14nm
You will not believe this, but the family was picking me up Friday evening from the airport and on the way home… Get this, for real, the wife asks me to cut her hair tomorrow. Now the three of you that read my stuff, know what happened before. I resisted, and firmly said ‘No’…The wife seeing my macho stance began appealing to my engineer’s… Read More
Variation-Aware Custom IC Design Best Practices
I’ve worked with Solido for 5 years, and it’s been a pleasure to watch the world’s top semiconductor companies and foundries adopt Solido software for their SPICE simulation flows.
Sub-28nm design starts are accelerating, growing from 150 in 2012 to 900 this year. The move to sub-28nm design nodes is being driven by consumer electronic… Read More
TSMC Updates: 20nm, 16nm, and 10nm!
*Spoiler Alert: The Sky is Not Falling*
The TSMC Technology Symposium last month provided a much needed technology refresh to counter aging industry experts (they make their living selling reports) who have been somewhat negative on the future of the fabless semiconductor ecosystem. If the sky wasn’t falling who would… Read More
FinFET Custom Design
At CDNLive, Bob Mullen of TSMC gave a presentation on their new custom FinFET flow, doing design, and verifying designs. At 16nm there are all sorts of relatively new verification problems such as layout dependent effects (LDE) and voltage dependent design rules. We had some of this at 20nm but like most things in semiconductor,… Read More
Handel Jones on FD-SOI vs FinFET
Handel Jones has a new white-paper out titled Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets. Handel has done an in-depth analysis of the wafer and die costs of the various approaches, bulk planar (what we have been doing up to now), FD-SOI and FinFET. The analysis… Read More
Handel Jones Predicts Process Roadmap Slips
At the SEMI ISS conference earlier this week, the last speaker in the technology challenges section was Handel Jones of IBS. I’ve known Handel since the mid-1980s when he came to VLSI Technology and told us we were losing money on 90% of the designs we were doing but our cost model was not good enough and so we didn’t even… Read More
New Frontiers in Scan Diagnosis
As we move down into more and more advanced process nodes, the rules of how we test designs are having to change. One big challenge is the requirement to zoom in and fix problems by doing root cause analysis on test data alone, along with the rest of the design data such as detailed layout, optical proximity correction and so on. But without… Read More
The Leading Edge Depends on What You Are Doing
At Semicon Japan a few days ago, Subi Kengeri of GlobalFoundries delivered the keynote. While he covered a number of topics, using Tokyo’s recent win of the 2020 Olympics as a hook, one major theme was the increasing importance of processes other than the bleeding edge digital processes that get all the news.
What is leading… Read More