Cliff Hou had two major appearances at DAC this year. He gave the opening day keynote…and he wrote the forward to Dan and my bookFabless: the Transformation of the Semiconductor Industry which about 1500 lucky people got a copy of courtesy of several companies, most notably eSilicon who sponsored the Tuesday evening post-conference party where we signed several hundred copies. You can still get a copy if you missed out, just click on the book cover on the top left hand side of the front page of SemiWiki.
Cliff’s keynote was about the future challenges of getting to 10nm and beyond. 14/16nm (they are basically the same despite the different numbers) are pretty much a done deal. Not yet in volume production but on track to get there later this year.
Cliff started by talking about mobile which is what drives semiconductor leading edge processes. Design innovation drives process innovation which enables more design innovation. As a result we have product innovation. It seems like we have always had smartphones but in fact the iPhone only came along 7 years ago. Up until then we had dumbphones although some marketing guy at Nokia cleverly called them feature phones to make them seem…almost smart.
Of course every process generation things get harder. Double patterning, FinFETs, multiple-patterning and so on. The big challenge is that as we approach 10nm, everything becomes more costly and so the economic driver that has been behind the semiconductor industry for the last few decades is weakening. It seems clear that the technical challenges can be overcome but at what cost?
There are two different sets of challenges getting to each new process node: the process issues, mostly around lithography, and the ecosystem issues.
- lithography: continue to scale 193nm immersion
- device: continue to deliver 25-30% speed gain at the same or reduced power
- interconnect: address escalating parasitics
- production: ramp volume in time to meet end-customer demand
- shortened development runway to meet product windows
Design and technology co-optimization used to be fairly straighforward. The best local optimum was also the best overall optimum: shortest wire length the best, best gate-density the best area scaling, best technology also best cost. But these rules don’t hold any more. Everything has to be co-optimized from process, EDA tools and IP. If one of these is not up in time then the designs cannot be completed and the fab will not be filled as soon as capacity is available. And given the cost of a fab at $5-8B then a fab that is not full costs a huge amount in depreciation.
The time to get to market is speeding up too. First test chip, first PDK, first shuttle, volume production, the big milestones on a new node are getting compressed. At 10nm, Cliff reckons they will be roughly half the time they had at 28nm. The cost of bringing the process up and building the fabs to run it makes it imperative to start recovering the cost as soon as possible.
Bottom line: this all requires much closer collaboration between all the partners to make everything work in a timely manner. This is the key to unlock 10nm and beyond and turn the vision into reality.