As we move down into more and more advanced process nodes, the rules of how we test designs are having to change. One big challenge is the requirement to zoom in and fix problems by doing root cause analysis on test data alone, along with the rest of the design data such as detailed layout, optical proximity correction and so on. But without putting being able to create and run additional tests or put the chip under an electron microscope. Since (digital) test these days is all scan based, this means analyzing scan test failure and “deducing” what the problem has to be Sherlock Holmes style.
One area of particular problem are intermittent problems due to patterning and double patterning issues. The test doesn’t fail all the time because sometimes the design prints just fine and sometimes it doesn’t, or sometimes the two patterns are well enough aligned that there is no problem and sometimes not. But this shows up as an extended period of low yield until the problem is fixed, which is a financial issue. For example the picture below is a GlobalFoundries 28nm test chip and you can see an area where optical interference has not been completely handled (28nm is not double patterned, this is an 80nm spacing I would assume).
Traditional failure analysis results in narrowing the problem down to a single logical net. By adding layout awareness, it can be narrowed down to a physical segment. Further analysis can sometimes narrow this down to a specific failure (bridge of two metals, open via, break in metal and so on) or more often a limited number of possible failures and their associated probabilities.
Root cause deconvolution (RCD) narrows things down more and gets rid of a lot of the noise, things that it cannot be based on a selection of die being analyzed and bayesian probability analysis. This then makes it possible to pick the best die for failure analysis (looking under an electron microscope for example to see what the layout actually looks like).
FinFETs and 14/16/20nm bring a new set of problems, one of which is that we are getting out of the resolution range of scanning electron microscopes (SEM) and tunneling electron microscopes are required (TEM). Plus a lot of the critical features are much smaller than before making manufacturing defects much more likely.
Mentor’s products that support this sort of analysis are Tessent Diagnosis and Tessent YieldAnalysis.
Mentor have a webinar entitled New Frontiers in Scan Diagnosispresented by Geir Eide. It is one of the ASM webinar series on electronic device failure and analysis. It goes into a lot more detail than here with lots more example, including lots more pictures of failures. The webinar is archived here.Share this post via: