SMIC N+2 in Huawei Mate Pro 60

Up until last December I was president and owner of IC Knowledge LLC, at the end of November, I sold IC Knowledge LLC to TechInsights. It has been interesting to become an insider at the world’s leading semiconductor reverse engineering and knowledge company. The latest SMIC N+2 analysis is an excellent example of TechInsight’s incredible capabilities in action. One of our salespeople in Asia was able to procure a Huawei Mate Pro 60 and hand carried it back to the lab in Ottawa. Our analysts have now extracted the processor and started running analysis on it, you can see the announcement about it here.

When we analyzed the previous N+1 device we found pitches in line with TSMC’s 10nm process but also more advanced features like single diffusion break and 6 track cells not seen until TSMC 7/7+ processes. The overall density of the dense logic on N+1 was slightly less than TSMC 7nm but close and we called N+1 a 7nm class device.

When I blogged about N+1 here, I noted that SMIC could further reduce the pitches even without EUV. TSMC’s original 7nm process was all done with optical multipatterning, the pitches were all achievable with double patterning except the fin pitch that required quadruple patterning. SMIC should be able to produce the same pitches without EUV.

Now we have the N+2 device in the early stages of analysis.

The N+2 Contacted Poly Pitch (CPP) and Metal 2 Pitches (M2P) are both tighter than N+1 but not as tight as TSMC 7nm, CPP in particular is relaxed from TSMC 7nm. CPP is made up of gate length (Lg), contact width (Wc) and gate to contact spacer thickness (Tsp). Lg is limited by leakage, Wc by parasitic resistance and Tsp by parasite capacitance. This indicates to me that SMIC is still struggling to achieve low leakage and low parasitic resistance and capacitance, M2P is much closer to TSMC 7nm. The overall high density logic transistor density for N+2 is intermediate between TSMC 7nm and 7nm+ making it a solid 7nm process. There is even some room to further shrink the pitches with double patterning to achieve something along the lines of TSMC 6nm densities in a future process (N+3?).

N+2 is an incremental improvement over N+1 moving from a borderline 7nm process to a solid 7nm process. This process is still within the limits of what optical double patterning can achieve and even has some room for additional shrinks.

To get more details and continue to follow this story as it unfolds, please go here.

I would like to thank Rajesh Krishnamurthy for helpful discussions and the whole TechInsights team for their outstanding work on this analysis.

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