Seven Reasons to Use FPGA Prototyping for ASIC Designs

There are four options for you to consider when choosing an FPGA prototyping approach:

The best practices include not starting FPGA prototyping while the RTL is still in flux, don’t expect a prototype to be used for hardware debug, and finally the challenges to partitioning can be taxing. If you opt for a turnkey prototyping solution then you don’t have to spend time becoming an FPGA expert.

Philipp Ampletzer from PRO DESIGN talked about six attributes of an ideal FPGA prototyping system:

• Flexibility, adaptability (both Xilinx and Altera)
• Performance and signal integrity
• Scalability and capacity (latest FPGA devices)
• Host interfaces
• User-friendly
• Price friendly, cost-performance ratio

It turns out that PRO DESIGN has a series of FPGA Prototyping products that use both Xilinx and Altera FGPAs, and you can start with a small configuration using a single FPGA, or scale up to a system with four FPGAs, or ultimately combing five boards for a total of 20 FPGAs. Here’s a photo of the FPGA Module SG280 which provides:

• Single Intel Stratix 10 FPGA providing up to 20M ASIC gates
• Up to 1,026 user I/O
• Up to 8 voltage regions
• Up to 1.0 Gbps single-ended point to point speed

The final presenter was Sachin Jadhav from Open-Silicon and he walked us through the typical ASIC design life cycle with 11 distinct steps showing where FPGA prototyping fits in:

Based on actual experience with FPGA prototyping at Open-Silicon, they look at five challenges:

• Selecting an FPGA Platform (capacity, I/Os, expected frequency, partitioning, turnkey or custom)
• Design Partitioning (automatic, manual)
• Optimum operating design frequency (choosing speed grade FPGAs, design IP placement, global clock, clock loading)
• Custom PHY’s
• Debugging (integrated RTL debugging)

Related blog – Open-Silicon Update: 125M ASICs shipped!

One case study was shared by Open-Silicon where they designed an ASIC for use in a professional camera system and partitioned their design across two Virtex 7 FPGAs with the following IP blocks:

This ASIC used 40 million gates and the FPGA prototype used manual partitioning with IOs in one FPGA and logic in the second FPGA, while communication between the two was with a SerDes. By using an FPGA prototype the design team saved some 5 months from the schedule and reached a first silicon success. Other achievements on this project included:

• Production quality software developed on FPGA prototype
• Custom PHY’s (HDMI, LVDS-TX, HSIFB, UHS-II) using FPGA resources
• Validated custom IP blocks with external devices prior to tape-out

Related blog – ARM and Open-Silicon Join Forces to Fight the IoT Edge Wars!

Summary
ASIC design teams are under immense pressure to meet product requirements and develop software before silicon is fabricated, so using an FPGA prototyping approach can help you do that by enabling early software driver development and even producing a proof of concept to investors. Maybe it’s the right time for your next ASIC project to start using an FPGA prototyping methodology.

To watch the archived webinar you can go here.