When TSMC advocates FD-SOI…

I found a patent recently (May,14 2013) granted to TSMC “Planar Compatible FDSOI Design Architecture”, the following sentences, directly extracted from this patent, advertise FDSOI design better than a commercial promotion! “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.” Nothing new here for Semiwiki readers… except that this enumeration of the advantages of SOI technology in respect with bulk planar is coming from TSMC…

In fact, the sentence mention “SOI substrates”, but when you look at the next paragraph, you find the definition of partially-depleted (PD) SOI transistor and fully-depleted (FD) SOI transistor, and their respective behavior and advantages:

• A PDSOI transistor is formed in an active region with an active layer thickness that is larger than the maximum depletion width. The PDSOI transistor therefore has a partially depleted body. PDSOI transistor have the merit of being highly manufacturable, but they suffer from floating body effects. Digital circuits, which typically have higher tolerance for floating body effects may employ PDSOI transistors.
  
• A FDSOI transistor is formed in an active region with an active layer thickness that is smaller than the maximum depletion width. FDSOI transistors avoid problems of floating body effects with the use of a thinner active layer thickness or a lighter body doping. Generally, analog circuitry performs better when designed using FDSOI devices than using PDSOI devices.

To illustrate this patent, TSMC is referring to a Baseband IC for mobile application, or maybe an integrated BB and Application Processor. In both cases many of the integrated IP, like memory cell or high speed SerDes, are based on analog circuitry, thus FDSOI clearly appears to be the best choice.

You may wonder why TSMC is highly promoting FDSOI, as we know that the foundry has not selected this technology. TSMC is supporting 28nm bulk planar, then 20nm (including double patterning for critical layers) and 16nm FinFET. So, why TSMC is doing such an advertising for FDSOI? Reading further, we can see:

“An FDSOI ASIC design in the same footprint as a bulk planar ASIC design provides several advantages over the bulk planar ASIC design. Adaptive body bias techniques are inefficient with bulk planar designs because of the PN junction forward bias issue and because junction leakage increases in the reverse bias condition. Therefore, planar technologies have to adopt voltage scaling techniques for power savings in single Vt designs.”

It look like that TSMC is willing to demonstrate that a FDSOI design can be portable to a bulk planar technology, providing that the power rails have been carefully designed, and this requirement is extensively described within the patent (in fact, it’s the core of the patent). We have highlighted in Semiwiki one of the important advantages linked with FDSOI technology: a dual Vt library can support a complete SoC design, allowing cost savings (number of masks and process steps is lower) and faster process turnaround time, when compared with four Vt on bulk planar, only bulk option to offer the same level of power savings than FDSOI.

But we still don’t know why TSMC has filled this patent. Is it because the company is willing to offer FDSOI as an additional process option to existing customers? In this case, this patent could be a way to minimize risk, showing to a customer moving to FDSOI that he could decide to come back to a bulk planar option, with no redesign because the “FDSOI ASIC design is in the same footprint as a bulk planar ASIC design”. By the way, TSMC offering FDSOI process option would be a scoop…

Another possibility would be that TSMC is not willing to support FDSOI, but certain existing ASIC customer willing to try FDSOI with TSMC competition, this patent would allow TSMC to keep the door opened, and these customers could come back to bulk planar ASIC processed at TSMC. This approach would be like a double sourcing, but between bulk planar and FDSOI.

TSMC has certainly carefully looked at FDSOI as a technology option, even if so far the company doesn’t support FDSOI. I am happy to see that a TSMC patent highlights the many technical advantages of FDSOI vs bulk planar, like absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance. In this advantage list, we can add potential cost savings (when SOI wafer price will go down), faster wafer fab cycle time and probably the most important, far better power efficiency, whether the SoC is designed for Networking infrastructure or mobile application processor. Will all these advantages be enough to compensate some current weaknesses, like customer fear in front of innovation and work in progress IP ecosystem, and finally pushing TSMC to join the ST and Samsung train?

From Eric Esteve from IPNEST

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