When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” :=) TSMC admitted that they hadn’t yet changed the tape-out checklist to forcibly include the DFM checks (CMP and LPC). This is what begs the question, what do you mean by mandatory?
What it really comes down to is this: if you tape out without these checks at 45/40 nm, you are taking a risk. If the design has yield issues and you didn’t run these checks, TSMC might wave the design off and insist that you take ownership of the yield issues. This is a huge risk. If the part comes out and has zero yield, and they find out it’s because of a level 1 hotspot in litho, or bridging due to CMP that you didn’t check for, then you have to eat the cost of a re-spin.
Most design teams doing large designs count on a certain number of re-spins before full production anyway, but to have to do one before you have any functional parts is a disaster. If you get parts that yield, but yield poorly, it can be just as bad, because these things can take a long time to find using traditional Low Yield Analysis, or FA. As someone who once had to re-spin a custom design due to a flaw in the incoming spec, I know the worst thing management can ask you before a re-spin is, “Are you sure that’s all that’s wrong with the design?” That one is guaranteed to cause sleepless nights.
At the time, TSMC pointed out that they had very little history on the 45/40 process and there was a definite need to do DFM analysis. TSMC also pointed out that DFM analysis might not be mandatory once the process is considered stable. By that time, the next process node will be in the hands of the early adopters, and DFM will be mandatory for that node, so the need for DFM won’t be going away anytime soon. The yield issues are real. Considering the total cost of developing a chip in 45/40 nm and the risks of really low yields, DFM tools seem like cheap insurance.
– Simon Favre, Technical Marketing Engineer for Calibre YieldAnalyzer