Lake Tahoe: The Center of ESD Innovation

Lake Tahoe: The Center of ESD Innovation
by glforte on 03-15-2015 at 1:00 pm

Almost anyone that is active in IC design will be “in touch” with Electrostatic Discharge (ESD) at some time (pun intended). Preventing ESD related IC failures remains something like black magic—at least it’s easy to get that feeling when you are trying to debug ESD failures. I/O and ESD layouts that resulted in excellent robustness… Read More


A Fill Solution for 20nm at TSMC

A Fill Solution for 20nm at TSMC
by glforte on 03-17-2014 at 5:12 pm

By Jeff Wilson, Mentor Graphics

We’ve talked about the new requirements for Fill in IC design for advanced nodes in previous blogs on this site. This time I’d like describe the fill solution that Mentor and TSMC have jointly developed to meet the requirements of fill for TSMC’s 20nm (N20) manufacturing process.

The traditional… Read More


Increasing Automotive Semiconductor Test Quality

Increasing Automotive Semiconductor Test Quality
by glforte on 06-17-2013 at 4:45 pm

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The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. At the same time, traditional fault models are becoming less effective at achieving desired silicon quality levels. Improvements in test solutions… Read More


Mentor Graphics User2User Conference

Mentor Graphics User2User Conference
by glforte on 04-05-2013 at 1:06 pm

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April 25, 2013, San Jose, CA

Click here to register.

Come hear Mentor Graphics CEO, Wally Rhines, 2013 Kaufman Award Winner,Chenming Hu, and Xilinx Senior VP,Victor Peng, at the User2User Conference in San Jose.

KEYNOTES
Organizing by Design
9:00am – 9:50am
Walden C. Rhines | CEO & Chairman | Mentor GraphicsRead More


Mentor at TSMC Technology Symposium

Mentor at TSMC Technology Symposium
by glforte on 03-29-2013 at 11:41 am

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TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage,… Read More


Wally Rhines, Victor Peng and Chenming Hu to Speak at Mentor User2User Conference

Wally Rhines, Victor Peng and Chenming Hu to Speak at Mentor User2User Conference
by glforte on 03-20-2013 at 10:29 am

This year’s Mentor Graphics user group meeting, User2User, will be held at the DoubleTree by Hilton in San Jose, California on April 25, 2013. The featured keynote presenters include…

  • Dr. Walden C. Rhines, CEO and Chairman of Mentor Graphics, talking about “Organizing by Design”
  • Victor Peng, Senior VP, Xilinx presenting on “T
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How Can You Work Better with Your Foundry?

How Can You Work Better with Your Foundry?
by glforte on 02-22-2013 at 5:40 pm

Image RemovedThe fabless revolution in the digital semiconductor industry is no more, with just a few integrated device manufacturers (IDMs) remaining on the playing field, it is now the normal way to do business. However, the learning curve for each new process node continues as it always has, with a host of new technical challenges… Read More


Get the Latest Info on DFM at the SPIE Litho Conference

Get the Latest Info on DFM at the SPIE Litho Conference
by glforte on 01-29-2013 at 2:12 pm

While the SPIE Advanced Lithography conference is best known for IC manufacturing, computational lithography, mask preparation and other back-end topics, there is also a significant amount of interest in Design for Manufacturing (DFM) at the conference because some litho issues are best (or only) addressed by modifying the… Read More


Mentor @ the TSMC Open Innovation Platform Forum

Mentor @ the TSMC Open Innovation Platform Forum
by glforte on 01-16-2013 at 6:16 pm

At TSMC’s Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described below with links to downloadable pdf presentation files.

Finding and Fixing Double Patterning Errors in
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GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs

GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs
by glforte on 11-28-2012 at 3:00 pm

Since the beginning of the semiconductor industry, improving the rate of yield learning has been a critical factor in the success silicon manufacturing. Each fab has dedicated yield teams that look at the yield of wafers manufactured the previous day and attempt to find the root cause of any unexpected “excursions.” In earlier… Read More