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How Philips Saved TSMC

How Philips Saved TSMC
by Daniel Nenni on 08-21-2023 at 6:00 am
Categories: Foundries, TSMC

TSMC Philips

TSMC and Philips have deep historical ties. In fact, TSMC may not have existed without Philips. In the 1980s TSMC was established as a joint venture with Philips Electronics, the government of Taiwan, and other private investors. Several semiconductor companies were approached by Morris Chang for funding including semiconductor giants Intel and Texas Instruments but neither chose to participate. Both Intel and TI are now TSMC customers so it came full circle.

Only Philips was willing to sign a joint venture contract with Taiwan to put up $58 million in exchange for a 27.5 percent stake in TSMC. The Taiwanese government provided another 48 percent of the startup capital for TSMC and the rest of the capital was raised from private investors. The government asked several of the island’s wealthiest families who owned firms that specialized in plastics, textiles, and chemicals, to put up the money. TSMC was really a Taiwanese enterprise rather than a normal start-up semiconductor company.

It wasn’t just the money, Philips also played a crucial role in the early days of TSMC by transferring semiconductor manufacturing technology, IP and patents to the newly-formed company and working closely as an investor, partner, and customer. Philips really was the first semiconductor company to go fab-light due to the rising costs of building and operating fabs.

Even though they had a minority stake, Philips had quite a bit of influence and even installed the first TSMC CEO James E. Dykes, who had previously worked for Philips North America. I will write more about James in the next installment.

However, over time, Philips reduced its stake in TSMC, and the two companies evolved in different directions. Philips shifted its primary focus to health technology while TSMC concentrated on becoming the most successful pure-play foundry in history, absolutely. The other semiconductor powerhouse Philips has historical ties to is ASML (ASML was a spinout of Philips Labs) but that is another story in itself.

Here is some background on Philips from ChatGPT-4:

“Founded in 1891 by Gerard Philips and his father Frederik in Eindhoven, the Netherlands, Philips, or Koninklijke Philips N.V. (Royal Philips), is a leading multinational conglomerate known for its diversified technology solutions. Initially starting as a company manufacturing incandescent lamps and other electrical products, Philips expanded over the decades into various sectors.

Here’s a brief overview of Philips’ trajectory over the years:

Early Days (1891 – 1920s): The company initially focused on producing carbon-filament lamps. They soon became one of the largest producers in Europe.

Radio and Electronics (1920s – 1940s): Philips entered the radio market in the 1920s. By the 1930s, they were one of the largest radio manufacturers in the world. They also started producing X-ray and radio technology during this period.

Post-war Era (1940s – 1960s): After World War II, Philips was involved in the revival of the Stirling engine. They also diversified into products like television sets and shavers during this period.

Electronics Expansion (1970s – 1990s): Philips expanded further into electronics, producing items like cassette tapes, CD players, and other home electronics. The company co-developed the Compact Disc (CD) with Sony.

2000s and beyond: In the 21st century, Philips started streamlining its operations to focus on health technology and personal health solutions. They sold off or spun off many non-core divisions, such as their semiconductor division (NXP Semiconductors) and their lighting division (Signify). The company’s primary focus has been on healthcare, diagnostic imaging, patient monitoring, health informatics, and personal care.

Throughout its history, Philips has been known for innovation and has been responsible for a number of significant technological advancements. The company operates globally and continues to be a major player in the fields it is active in.“

The Dutch had an even deeper connection to Taiwan dating back hundreds of years. Here is a 10 minute history video that covers it nicely and is well worth watching:

Next up: TSMC’s first CEO James E. Dykes and the Taiwan Semiconductor Outlook (May 1988).

Also Read:

How Taiwan Saved the Semiconductor Industry

Morris Chang’s Journey to Taiwan and TSMC

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Morris Chang’s Journey to Taiwan and TSMC

Morris Chang’s Journey to Taiwan and TSMC
by Daniel Nenni on 08-14-2023 at 6:00 am
Categories: Foundries, TSMC
2 Comments

Morris Chang 2023

High volume manufacturing is a 24/7 business with 12 hour shifts. You don’t always get to pick the shifts you want and you must cover for others when they can’t. It’s a challenging career and not for the faint of heart like myself.

In the 1980s and 1990s I spent time in Japan working with some of the top Japanese semiconductor manufacturers. It was an amazing experience but I walked away wondering how the US would be able to compete. The Japanese people I met worked very hard to honor their families and country. Back in the United States we worked 9-5 for a paycheck. Morris Chang knew this from his experience at TI and that is why he headed to Taiwan.

As I have written, Taiwan’s early start into semiconductors did not begin with Morris Chang but he does figure in prominently in Taiwan’s rise to dominance. Here is a brief biography of Morris (ChatGPT 4.0):

“Morris Chang (张忠谋) is widely recognized as the father of Taiwan’s semiconductor industry. Born in 1931 in Ningbo, China, Chang moved to the U.S. in the late 1940s, where he pursued higher education in the field of physics and engineering.

Here are a few key points about Morris Chang:

  1. Education: Morris Chang holds degrees from several esteemed institutions. He received a B.S. and M.S. in Mechanical Engineering from the Massachusetts Institute of Technology (MIT) and a Ph.D. in Electrical Engineering from Stanford University.
  2. Texas Instruments: Before his endeavors in Taiwan, Chang worked at Texas Instruments (TI) in the United States for 25 years. During his tenure there, he held various senior positions including Group Vice President of the Worldwide Semiconductor Group.
  3. Taiwan Semiconductor Manufacturing Company (TSMC): In 1987, Chang founded the Taiwan Semiconductor Manufacturing Company (TSMC). TSMC is the world’s first dedicated semiconductor foundry, meaning it manufactures chips for other companies without designing its own products. This business model transformed the global semiconductor industry, enabling a myriad of fabless semiconductor companies to focus on chip design without having to invest in expensive manufacturing facilities.
  4. Economic Impact: Under Chang’s leadership, TSMC became a cornerstone of Taiwan’s IT industry, propelling the country into a major role in the global semiconductor market. Taiwan’s importance in chip manufacturing can’t be overstated, with TSMC at the forefront of cutting-edge semiconductor technology and production.
  5. Retirement: Chang retired from TSMC in 2018, but his influence in the semiconductor world and his legacy as a pioneer in the foundry business model will persist for years to come.
  6. Recognition: Chang has received numerous awards and honors over the years in recognition of his contributions to the semiconductor industry and his visionary leadership.

In summary, Morris Chang is a seminal figure in the semiconductor industry, especially in the foundry business model. His leadership and strategic vision not only transformed the industry but also elevated Taiwan’s standing in the global tech ecosystem.“

From a semiconductor insider’s point of view, there is a lot more to this story. Morris started his education at Harvard but MIT turned out to be more to his liking both financially and technically. For engineers, MIT was the place to be and Morris was an engineer at heart. Morris chose mechanical engineering but he quickly became obsessed with the transistor during his first job right out of college.

After graduating from MIT (1955) Morris went to work for Sylvania, a company with a long history in lighting and electronics. After 3 years Morris wanted to go where the transistor innovation was and that was Texas Instruments. His dream was to be the head of the central research labs at TI but Morris did not have a PhD, or even a degree in electrical engineering.  In fact, he twice failed a qualifying exam for a doctoral degree at M.I.T.

Morris first worked in the germanium transistor business which would soon be surpassed by the silicon transistor. TI was IBMs major supplier (20% of TI’s revenue) and Morris was in charge of the IBM program. Getting yields ramped up was the first big challenge for Morris. He burned the midnight oil and cracked the yield code and became a hero. Morris was promoted to the head of the germanium transistor program and in 1963 he was sent to Stanford to get his PhD for further advancement. He Finished the PhD program in a record time (2.5 years) while still spending time at TI.

When Morris returned to TI full time, germanium was no longer leading edge technology so Morris took a leadership position with the TI IC group. Morris’s influence grew and in 1973 he became head of the semiconductors group and again became a hero. TI was the king of TTL (Transistor – Transistor Logic)  with a 60% market share and more than $1B in revenue, but TTL was soon replaced by MOS and TI lost the MOS race.

SemiWiki: Texas Instruments and the TTL Wars

Morris’s downfall at TI was MOS memory and microprocessors. Other companies caught up with TI (Mostek) and in some cases surpassed them. Microprocessors became the next big thing and TI had the first microprocessor patent, not Intel or Motorola. When IBM chose the Intel 8088 microprocessor for their first personal computer over the TI TMS9900 and the Motorola 6800 (amongst others), Morris took this as a personal defeat.

In 1977 Morris’s departure from TI officially started when he was removed as Group VP of Semiconductors and became Group VP of Consumer Products, a somewhat troubled business at the time (calculators and toys). Morris was then moved to head of corporate quality and his fall from grace was complete. Morris wasn’t fired from TI but his departure was not unexpected.

Morris then spent a difficult two years (1984-86) at General Instruments under CEO Frank Hickey before calling it quits and heading to Taiwan. I was a field engineer for GI during the Hickey era (1979-82)  and it was a tumultuous time for the company, absolutely.

Bottom Line: The work ethic and experience Morris developed through his career with innovative electronic and semiconductor companies was the perfect foundation for the customer centric pure-play foundry model that is TSMC. It should be noted that TI is today a semiconductor powerhouse, one of the longest standing semiconductor companies in the world. TI is also a long standing customer of TSMC.

To be continued…. How Philips saved TSMC!

Also Read:

How Taiwan Saved the Semiconductor Industry

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How Taiwan Saved the Semiconductor Industry

How Taiwan Saved the Semiconductor Industry
by Daniel Nenni on 08-07-2023 at 6:00 am
Categories: Foundries, TSMC
4 Comments

Taiwan USA

Now that semiconductors are front page news and a political football, I would like to write more about how we got to where we are today to better understand where semiconductors will go tomorrow. I will start this article with a provocative quote that really made me laugh and will put some context to what I am trying to accomplish here:

Trump accuses Taiwan of taking away America’s semiconductor business “Taiwan, they took our business away. We should have stopped them. We should have taxed them. We should have tariffed them,” said Donald Trump, Fox News, July 2023.

I know, American politics is an acquired taste but it is funny just the same. We already covered the fabless transformation in our book “Fabless: The Transformation of the Semiconductor Industry” so let’s start with a quick look at the history of the semiconductor industry in Taiwan (GPT 4.0):

The semiconductor industry in Taiwan has a rich history that spans several decades, starting from the 1970s to the present day. The industry has played a crucial role in Taiwan’s economic transformation from an agrarian economy to one of the world’s top high-tech industrialized nations.

Here are some of the key milestones:

“Formation of Electronics Research and Service Organization (ERSO): In 1973, the Taiwanese government established ERSO under the Industrial Technology Research Institute (ITRI). Its aim was to develop the electronics industry in Taiwan and provide a platform for semiconductor research and development.

Birth of Taiwan Semiconductor Manufacturing Company (TSMC): In 1987, TSMC, the world’s first dedicated semiconductor foundry, was founded by Dr. Morris Chang. The establishment of TSMC initiated the foundry model in the global semiconductor industry, which separated the manufacturing and design aspects of chip production. This allowed fabless companies to focus on designing innovative chip solutions without the need for significant capital investments in manufacturing facilities.

Hsinchu Science and Industrial Park: The Taiwanese government established this park in 1980 to serve as a hub for high-tech companies. It now houses numerous semiconductor companies and has played a significant role in the growth of Taiwan’s semiconductor industry.

Expansion of other major semiconductor companies: Over the years, several other Taiwanese companies have become key players in the global semiconductor industry. These include United Microelectronics Corporation (UMC), the world’s second-largest pure-play semiconductor foundry, MediaTek, a leading fabless semiconductor company, and ASE Technology Holding Co., the world’s largest provider of independent semiconductor manufacturing services in assembly and test.

Leadership in Advanced Process Technology: In recent years, TSMC, in particular, has emerged as a global leader in advanced process technologies, successfully achieving mass production at ever smaller node sizes (7nm, 5nm, 3nm and planning for 2nm and beyond). This has placed Taiwan at the forefront of the global semiconductor industry.

While this summary provides a brief overview, the history of Taiwan’s semiconductor industry is rich and complex, driven by strategic government initiatives, visionary leadership, strong educational programs, and the rise of the global digital economy. As of 2023, Taiwan is one of the world’s largest and most important centers for semiconductor manufacturing.”

Great summary, here is a little color on what happened. When I joined the semiconductor industry in the 1980s it was a challenging decade. Mini computer companies such as IBM, Hewlet-Packard, Digital Equipment, Data General, Prime Computer, and Wang all had their own fabs all over the United States. Unfortunately, due to over regulation (especially here in California) and the inability to hire skilled workers (sound familiar?), manufacturing of all types left the US for more friendly countries.

Additionally, in the 1980s, there were quite a few economic ups and downs including the crash of 1985. Keeping these very expensive fabs running was difficult which spawned the IDM foundry business where US and Japanese semiconductor companies accepted designs from outside customers for contract manufacturing to fill their fabs.

One of the first big fabless companies to do this was FPGA vendor Xilinx (founded in 1984, now owned by AMD). Sieko Epson (Japan) was Xilinx’s first IDM foundry partner. Xilinx quickly outgrew the relationship and moved to UMC and then TSMC which is where they are today.

Clearly IDM foundries were a stop-gap solution back then since they routinely competed with customers and the foundry business had lower margins than the products they manufactured internally so those products always had priority in the fabs.

Also in the 1980s, the ASIC business model was developed by VLSI Technology (founded in 1979) and LSI Logic (founded in 1980). VLSI and LSI accepted designs from fabless companies and manufactured them using internal fabs. But again the cost of the fabs was prohibitive. The ASIC business model is again thriving but it is now populated by fabless ASIC companies who do the design and manage manufacturing through the foundries.

Bottom line: The early IDM foundries and ASIC companies created the perfect storm for the pure-play foundry business model that fully evolved in the 1990s and that is where Dr. Morris Chang comes in.

To be continued… Morris Chang’s journey to Taiwan.

Also Read:

Morris Chang’s Journey to Taiwan and TSMC

Intel Enables the Multi-Die Revolution with Packaging Innovation

TSMC Redefines Foundry to Enable Next-Generation Products

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TSMC Redefines Foundry to Enable Next-Generation Products

TSMC Redefines Foundry to Enable Next-Generation Products
by Mike Gianfagna on 06-30-2023 at 6:00 am
Categories: AI, Foundries, TSMC
7 Comments

TSMC Redefines Foundry to Enable Next Generation Products

For many years, monolithic chips defined semiconductor innovation. New microprocessors defined new markets, as did new graphics processors, and cell-phone chips. Getting to the next node was the goal, and when the foundry shipped a working part victory was declared. As we know, this is changing. Semiconductor innovation is now driven by a collection of chips tightly integrated with new packaging methods, all running highly complex software. The implications of these changes are substantial. Deep technical skills, investment in infrastructure and ecosystem collaboration are all required. But how does all of this come together to facilitate the invention of the Next Big Thing? Let’s look at how TSMC redefines foundry to enable next-generation products.

What Is a Foundry?

The traditional scope of a foundry is wafer fabrication, testing, packaging, and delivery of a working monolithic chip in volume. Enabling technologies include a factory to implement a process node, a PDK, validated IP and an EDA design flow. Armed with these capabilities, new products are enabled with new monolithic chips. All this worked quite well for many decades. But now, the complexity of new product architectures, amplified by a software stack that is typically enabling AI capabilities, demands far more than a single, monolithic chip. There are many reasons for this shift from monolithic chip solutions and the result is a significant rise in multi-die solutions.

Much has been written about this shift in the innovation paradigm it enables. In the interest of time, I won’t expand on that here. There are many sources of information that explain the reasons for this shift. Here is a good summary of what’s happening.

The bottom line of all this is that the definition of product innovation has changed substantially. For many decades, the foundry delivered on the technology needed to drive innovation – a new chip in a new process. The requirements today are far more complex and include multiple chips (or chiplets) delivering various parts of the new system’s functionality. These devices are often accelerating AI algorithms. Some are sensing the environment, or performing mixed signal processing, or communicating with the cloud. And others are delivering massive, local storage arrays.

All this capability must be delivered in a dense package to accommodate the required form factor, power dissipation, performance, and latency of new, world-changing products. The question to pose here is what has become of the foundry? Delivering the enabling technology for all this innovation requires a lot more than in the past. Does the foundry now become part of a more complex value chain, or is there a more predictable way?  Some organizations are stepping up. Let’s examine how TSMC redefines foundry to enable next-generation products.

The Enabling Technologies for Next Generation Products

There are new materials and new manufacturing methods required to deliver the dense integration required to enable next-generation products. TSMC has developed a full array of these technologies, delivered in an integrated package called TSMC 3DFabric™.

Chip stacking is accomplished with a front-end process called TSMC-SoIC™ (System on Integrated Chips). Both Chip on Wafer (CoW) and Wafer on Wafer (WoW) capabilities are available. Moving to back-end advanced packaging, there are two technologies available. InFO (Integrated Fan-Out) is a chip-first approach that provides redistribution layer (RDL) connectivity, optionally with local silicon interconnect. CoWoS® (Chip on Wafer on Substrate) is a chip-last approach that provides a silicon interposer or an RDL interposer with optional local silicon interconnect.

All of this capability is delivered in one unified package. TSMC is clearly expanding the meaning of foundry. In collaboration with IP, substrate and memory suppliers, TSMC also provides an integrated turnkey service for end-to-end technical and logistical support for advanced packaging. The ecosystem tie-in is a critical ingredient for success. All suppliers must work together effectively to bring the Next Big Thing to life. TSMC has a history of building strong ecosystems to accomplish this.

Earlier, I mentioned investment in infrastructure. TSMC is out in front again with an intelligent packaging fab. This capability makes extensive use of AI, robotics and big data analytics. Packaging used to be an afterthought in the foundry process. It is now a centerpiece of innovation, further expanding the meaning of foundry.

Toward the Complete Solution

All the capabilities discussed so far bring us quite close to a fully integrated innovation model, one that truly extends what a foundry can deliver. But there is one more piece required to complete the picture. Reliable, well-integrated technology is a critical element to successful innovation, but the last mile for this process is the design flow. You need to be able to define what technologies you will use, how they will be assembled and then build and verify a model of your semiconductor system and verify it will work before building it.

Accomplishing this requires the use of tools from several suppliers, along with IP and materials models from several more. It all needs to work in a unified, predictable way. For the case of advanced multi-chip designs, there are many more items to address. The choice of active and passive dies, how they are connected, both horizontally (2.5D) and vertically (3D) and how they will all interface to each other are just a few of the new items to consider.

I was quite impressed to see TSMC’s announcement at its recent OIP Ecosystem Forum to address this last mile problem. If you have a few minutes, check out Jim Chang’s presentation. It is eye-opening.

The stated mission for this work is:

  • Find a way to modularize design and EDA tools to make the 3DIC design flow simpler and efficient
  • Ensure standardized EDA tools and design flows are compliant with TSMC’s 3DFabric technology
3Dblox Standard

With this backdrop, TSMC introduced the 3Dblox™ Standard. This standard implements a language that provides a consistent way specify all requirements for a 2.5/3D design. It is an ambitious project that unifies all aspect of 2.5/3D design specification, as shown in the figure.

Thanks to TSMC’s extensive OIP ecosystem, all the key EDA providers support the 3Dblox language, making it possible to perform product design in a unified way, independent of a specific tool flow.

This capability ties it all together for the product designer. The Next Big Thing is now within reach, since TSMC redefines foundry to enable next-generation products.

Also Read:

TSMC Doubles Down on Semiconductor Packaging!

TSMC Clarified CAPEX and Revenue for 2023!

TSMC 2023 North America Technology Symposium Overview Part 3

 

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TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am
Categories: Chiplet, Foundries, TSMC
4 Comments

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the increasing investment in packaging TSMC is making. The fab is ready for mass production of the TSMC SoIC packing technology. Remember, when TSMC says mass production they are talking about Apple iPhone sized mass production, not engineering samples or internal products.

Today packaging is an important part of a semiconductor foundry offering. Not only is it a chip level product differentiator, it will take foundry customer loyalty to a whole new level. This will be critical as the chiplet revolution takes hold making it much easier for customers to be foundry independent. Chiplet packaging however is very complex and will be foundry specific which is why TSMC, Intel, and Samsung are spending so much CAPEX to secure their place in the packaging business.

The TSMC 3DFabric is a comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies:

  • TSMC 3DFabric consists of a variety of advanced 3D Silicon Stacking and advanced packaging technologies to support a wide range of next-generation products:
    • On the 3D Si stacking portion, TSMC is adding a micro bump-based SoIC-P in the TSMC-SoIC®family to support more cost-sensitive applications.
    • The 2.5D CoWoS®platform enables the integration of advanced logic and high bandwidth memory for HPC applications, such as AI, machine learning, and data centers. InFO PoP and InFO-3D support mobile applications and InFO-2.5D supports HPC chiplet integration.
    • SoIC stacked chips can be integrated in InFO or CoWoS packages for ultimate system integration.
  • CoWoS Family
    • Aimed primarily for HPC applications that need to integrate advanced logic and HBM.
    • TSMC has supported more than 140CoWoS products from more than 25
    • All CoWoS solutions are growing in interposer size so they can integrate more advanced silicon chips and HBM stacks to meet higher performance requirements.
    • TSMC is developing a CoWoS solution with up to 6Xreticle-size (~5,000mm2) RDL interposer, capable of accommodating 12 stacks of HBM memory.
  • InFO Technology
    • For mobile applications, InFO PoP has been in volume production for high-end mobile since 2016 and can house larger and thicker SoC chips in smaller package form factor.
    • For HPC applications, the substrateless InFO_M supports up to 500 square mm chiplet integration for form factor-sensitive applications.
  • 3D Silicon stacking technologies
    • SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
    • SoIC-X is based on bumpless stacking and is aimed primarily at HPC applications. Its chip-on-wafer stacking schemes feature 4.5 to 9μm bond pitch and has been in volume production on TSMC’s N7 technology for HPC applications.
    • SoIC stacked chips can be further integrated into CoWoS, InFo, or conventional flip chip packaging for customers’ final products.

“Chiplet stacking is a key technology for improving chip performance and cost-effectiveness. In response to the strong market demand for 3D IC, TSMC has completed early deployment of advanced packaging and silicon stacking technology production capacity, and offers technology leadership through the 3DFabricTM platform,” said Dr. Jun He Vice President, Operations / Advanced Packaging Technology & Service, and Quality & Reliability. “With the production capacity that meets our customers’ needs, we will unleash innovation together and become an important partner that customers trust in the long term.”

TSMC’s customer centric culture will be a big part of the chiplet packaging revolution. By working with hundreds of customers you can bet TSMC will have the most comprehensive IC packaging solutions available for fabless and systems companies around the world, absolutely.

TSMC Press Release:
TSMC Announces the Opening of Advanced Backend Fab 6, Marking a Milestone in the Expansion of 3DFabric™ System Integration Technology

Also Read:

TSMC Clarified CAPEX and Revenue for 2023!

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

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TSMC Clarified CAPEX and Revenue for 2023!

TSMC Clarified CAPEX and Revenue for 2023!
by Daniel Nenni on 06-06-2023 at 2:00 pm
Categories: Events, Foundries, TSMC
4 Comments

TSMC HQ Taiwan

TSMC clarified CAPEX and revenue for 2023 last night at the Annual Shareholders Meeting. Last year TSMC guided up during this meeting but this year they guided down. CAPEX was guided down to the lower end of $36B-$32B.  Revenue was guided down from low-single to mid-single digit so maybe down another percent or two. The TSMC Jan – May 2023 revenue report indicates a decrease of 1.9 percent compared to the same period in 2022 so I think TSMC is being very conservative here.

Other foundries may not be as fortunate. Globalfoundries is already -5% in Q1 and UMC is -17% Jan-May 2023. In contrast TSMC started the year strong with +16% in January and +11% in February. Things turned bad in March with -15% and April -14%. At the TSMC Symposium CC Wei joked about his horrible forecasting but coming off the strongest year in the history of TSMC it was not a surprise.

“The year 2022 was a landmark year for TSMC. Supported by our strong technology leadership and differentiation, we delivered a thirteenth-consecutive year of record revenue, with strong profitable growth. Our 2022 annual revenue increased 33.5% year-over-year in U.S. dollar terms, while our EPS rose to NT$39.20, nearly tripling over the past three years.”

A landmark year indeed. TSMC manufactured 12,698 products for 532 customers in 2022. Hopefully we can all recognize this incredible achievement. Unfortunately, 2023 will also be a landmark year for a YoY decline and the pandemic is still to blame.

TSMC predicts that the second half of 2023 will improve so we may be at the bottom. 2024 also looks very promising but of course it is too soon to tell. According to the  World Semiconductor Trade Statistics, the global semiconductor industry is forecasted to grow 11.8% to $576B in 2024 with a major rebound expected in the memory segment, a surge of about 40% from last year.

The other news from the meeting echoed the Symposium which is good news:

 “In Taiwan, our N3 has just entered volume production in Tainan Science Park. We are also preparing for N2 volume production starting in 2025, which will be located in Hsinchu and Taichung Science Parks. In the U.S., we are in the process of building two advanced semiconductor fabs in Arizona, with N4 and N3 process technology, respectively. We are also building a 12-inch specialty technology fab in Kumamoto, Japan.”

TSMC was crystal clear in the reasoning for building fabs around the world. TSMC’s business model has always been customer centric and customers want fabs near their customers. This customer demand is not just for semiconductor manufacturing, other manufacturing is localizing as well, and again it is a direct result of the pandemic which broke supply chains around the world.

“N2 technology development is on track, with risk production scheduled in 2024 and volume production in 2025. Our 2-nanometer technology will be the most advanced semiconductor technology in the industry in both density and energy efficiency when it is introduced.”

Interesting wording here and I do agree N2 will be denser and more power efficient than Intel 20A or Samsung 3nm. I would also add more cost effective as no one in the foundry business has the economies of scale to match TSMC.

One thing you have to remember is that when TSMC says volume N2 production in 2025 that means Apple which is a multi-billion transistor SoC shipped by the millions. TSMC is not talking about internal product, engineering samples or chiplets. The mainstream media misses this point every time. Either they are ignorant or they are intentionally besmirching TSMC to get clicks. Either way it is unethical, my opinion.

“To help customers unleash their product innovations with fast time-to-market, TSMC provides customers with comprehensive infrastructure needed to optimize design productivity and cycle times. TSMC continues to expand our Open Innovation Platform® (OIP), providing over 55,000 items of libraries and silicon IP portfolio, more than 43,000 technology files, and over 2,900 process design kits, from 0.5-micron to 3-nanometer in 2022.”

As most people know I have been part of this ecosystem since it started so I know it better than most. The one thing that I would add here is that with the overwhelming success of TSMC N3, the ecosystem has never been stronger for TSMC so there is significant momentum for the N2 transition, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

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Investing in a sustainable semiconductor future: Materials Matter

Investing in a sustainable semiconductor future: Materials Matter
by Daniel Nenni on 05-31-2023 at 6:00 am
Categories: EMD Electronics, Foundries, Semiconductor Services, TSMC

EMD LinkedIn Twitter Materials Matter

In 2020 TSMC established its Net Zero Project with a goal of net zero emissions by 2050. I remember wondering how could this possibly be done before 2050 or at all for that matter. After working with TSMC for 20+ years I have learned never to bet against them on any topic and green manufacturing is one of them, absolutely.

TSMC presented on green manufacturing at the recent symposium in Silicon Valley. Clearly energy and water resources are critical parts of any net zero project but carbon emissions are also a of great importance and that means materials. In regards to semiconductor manufacturing materials we have experts here on SemiWiki.

EMD Electronics has a presence in 66 countries and over 100 years of invaluable experience in the electronic materials space delivering a broad portfolio of semiconductor and display materials for cutting-edge electronics.

EMD Electronics recently published a paper: INVESTING IN A SUSTAINABLE SEMICONDUCTOR FUTURE – MATERIALS MATTER.

It is a very interesting comprehensive look at innovative sustainable semiconductor materials techniques that decrease carbon emissions, improve resource efficiency and productivity, and highly contribute to achieving net zero semiconductor.

“It is amazing where collaboration can take us. Sustainability is no longer the result of individuals; only by working together can we get closer to our goals for a sustainable future! Brita Grundke, Head of Sustainability, EMD Electronics”

Here is the introduction. This paper is freely available and well worth the read for semiconductor professionals at all levels:

Emissions from semiconductor manufacturing are a growing segment of global greenhouse gas (GHG) emissions. There are two reasons behind this trend. First, the demand for semiconductor chips is growing. Our technology appears in everything from mobile phones to automobiles, where the number of chips per vehicle increases every year. Data storage, which relies on the semiconductor industry, is exploding. Second, today’s manufacturing processes have more deposition and etch steps than ever. Each step consumes water and electricity and creates GHG emissions.

Semiconductor companies large and small talk about achieving climate neutrality by 2030. That sounds like a great goal. But merely achieving that goal won’t solve the emissions problem. How we get there matters.

Buying carbon offsets is an easy way out. It isn’t the best long-term answer, because many offsets are not as effective as they claim to be. Some may even make the problem worse, defeating the purpose [1]. And relying on offsets can make internal actions seem less pressing. It is best to see offsets as a temporary or last-choice option.

Semiconductor industry leaders are, of course, doing more than buying offsets. They are investing in renewable energy, improving the energy efficiency of their processes, and finding ways to reduce waste. These actions are helpful, and we must do more. Despite modest success in reducing emissions per wafer or per revenue, demand for semiconductor chips is growing faster than the improvements can handle. We need more drastic reductions, and that starts by examining the sources.

Bottom Line: Climate change is real and semiconductor manufacturing is under a microscope now that it is being regionalized due to the shortages and supply chain issues we suffered during the pandemic. If you really want to know why semiconductor manufacturing left the US it was due to the Environmental protection Agency crack down on water, ground, and air pollution. I grew up in Silicon Valley so I had front row seat to the environmental issues of semiconductor manufacturing. Now that semiconductor manufacturing is coming back to the US and other parts of the world sustainability is front and center once again.

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Chiplet Interconnect Challenges and Standards

Chiplet Interconnect Challenges and Standards
by Daniel Payne on 05-25-2023 at 10:00 am
Categories: Chiplet, EDA, Synopsys, TSMC

Multi die IP min

For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s more cost effective to use two or more smaller chiplets designed in a variety of technology nodes. Taking the multi-die system path introduces new chiplet interconnect challenges:

  • Reliable connectivity
  • High bandwidth
  • Low power
  • Low latency
  • Standards support

Fortunately for the industry there’s been a collective effort to develop standards, and the Universal Chiplet Interconnect Express™ (UCIe™) has gained traction by enabling package-level integration through a die-to-die interconnect along with a connectivity protocol, so that multiple vendors can grow an ecosystem through interoperability. UCIe covers three stack layers, and the PHY layer defines the electrical interface.

Synopsys has been delivering IP for many years now across many domains, like: Interface, Foundation, Processor, Security, Analog, Subsystems. They’ve also joined the UCIe Consortium, contributing to the specification of the standard. There’s a UCIe PHY IP from Synopsys, along with a UCIe Controller IP and verification IP.

Synopsys Multi-die IP

In March 2023 Synopsys announced that their UCIe PHY IP had a tape-out on the TSMC N3E process node.

For reliable connectivity the UCIe standard has up to 8 spare pins per direction, allowing repair of the functional links.

Link Repairs

Variations in the die-to-die interface signals are monitored by Signal Integrity Monitors (SIM), then the Monitoring, Test and Repair controller can determine the health of the multi-die system for predictive maintenance of the links. Synopsys has the Silicon Lifecycle Management tools to monitor the UCIe interface while its operating, detecting soft or hard errors.

Synopsys Monitoring, Test and Repair (MTR) controller

Bandwidth for UCIe using the Synopsys PHY IP is up to 5Tbps/mm efficiency. The Controller IP supports streaming protocols as well as PCI Express and CXL protocols, delivering secure, low-latency data.

Coming up to speed on the UCIe specification takes precious engineering time, so re-using protocol verification IP is going to save your team valuable time to market. Verification IP running on a software simulator provides a good start, then adding hardware emulation with Synopsys ZeBu and prototyping with Synopsys HAPS Platform offer more time savings to debug the whole system running software.

Routing the UCIe signals between dies is automated by the Synopsys 3DIC Compiler tool, and it works for 2.5D chiplets.

Summary

Systems engineers today still have to decide between two approaches for implementation, the traditional single-chip SoC, or the multi-die system. EDA vendors like Synopsys have long been automating the EDA tasks for a single-chip SoC, and they’ve also extended their automation into the realm of 2.5D by developing new EDA tools, verification and IP for multi-die systems.

The interconnect challenges of multi-die systems have been addressed through standardization efforts like UCIe, which lowers the risks for new projects considering chiplet-based systems. Synopsys is one of the few EDA and IP vendors with such broad support of multi-die systems.

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Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
by Daniel Nenni on 05-04-2023 at 6:00 am
Categories: 5G, AI, Alphawave Semi, Chiplet, Events, IP, TSMC

Alphawave Semi 3nm Eye Diagram

There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node in the history of the TSMC FinFET family, absolutely.

(Graphic: TSMC)

In order to tape-out to 3nm you need IP and high speed SerDes IP is critical for HPC applications such as AI which is now the big semiconductor driver for leading edge silicon. Enabling chiplets at 3nm is also a big deal and that is the focus of this well worded announcement:

Successful launch of 3nm connectivity silicon brings chiplet-enabled custom silicon platforms to the forefront Alphawave Semi 3nm Eye Diagram

(Graphic: Business Wire)

LONDON, United Kingdom, and TORONTO, Canada – April 25, 2023 – Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity for the world’s technology infrastructure, today announced the bring-up of its first connectivity silicon platform on TSMC’s most advanced 3nm process with its ZeusCORE Extra-Long-Reach (XLR) 1-112Gbps NRZ/PAM4 serialiser-deserialiser (“SerDes”) IP.

An industry-first live demo of Alphawave Semi’s silicon platform with 112G Ethernet and PCIe 6.0 IP on TSMC 3nm process will be unveiled at the TSMC North America Symposium in Santa Clara, CA on April 26, 2023.

The 3nm process platform is crucial for the development of a new generation of advanced chips needed to cope with the exponential growth in AI generated data, and enables higher performance, enhanced memory and I/O bandwidth, and reduced power consumption. ZeusCORE XLR Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the Alphawave Semi product portfolio and on the 3nm process will pave the way for the development of future high performance AI systems. It is a highly configurable IP that supports all leading edge NRZ and PAM4 data center standards from 1112 Gbps, supporting diverse protocols such as PCIe Gen1 to Gen6 and 1G/10G/25G/50G/100 Gbps Ethernet.

This flexible and customizable connectivity IP solution together with Alphawave Semi’s chiplet-enabled custom silicon platform which includes IO, memory and compute chiplets, allows end-users to produce high performance silicon specifically tailored to their applications. Customers can benefit from Alphawave Semi’s application optimized IP-subsystems and advanced 2.5D/3D packaging expertise to integrate advanced interfaces such Compute Express Link (CXLTM), Universal Chiplet Interconnect ExpressTM (UCIeTM), High Bandwidth Memory (HBMx), and Low-Power Double Data Rate DRAM (LP/DDRx/) onto custom chips and chiplets.

“We are thrilled to be one of the first companies to successfully demonstrate our highest performance silicon platform with our XLR 112G Ethernet and PCIE6.0 SerDes IP on TSMC’s most advanced 3nm technology”, said Tony Pialis, CEO and co-founder of Alphawave Semi. “This represents a significant stepforward in our execution of Alphawave Semi’s strategy to be a vertically-integrated semiconductor leader in high-speed connectivity. Thanks to our rapidly growing partnership with TSMC through the Open Innovation Platform© (OIP), we continue to deliver innovative, high-performance custom silicon and IP solutions to our customers in data center, compute, networking, AI, 5G, autonomous vehicles, and storage applications.”

“Alphawave Semi continues to see growing demand from our hyperscaler customers for purpose-built silicon with very high-speed connectivity interfaces, fueled by an exponential increase in processing of AI-generated data”, said Mohit Gupta, SVP and GM, Custom Silicon and IP, Alphawave Semi. “We’re engaging our leading customers on chiplet-enabled 3nm custom silicon platforms which include IO, memory, and compute chiplets. Our Virtual Channel Aggregator (VCA) partnership with TSMC has provided invaluable support, and we look forward to accelerating our customers’ high-performance designs on TSMC’s 3nm process.”

About Alphawave Semi

Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

Alphawave Semi at the Chiplet Summit

Alphawave IP is now Alphawave Semi for a very good reason!

High-End Interconnect IP Forecast 2022 to 2026

 

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TSMC 2023 North America Technology Symposium Overview Part 5

TSMC 2023 North America Technology Symposium Overview Part 5
by Daniel Nenni on 04-27-2023 at 10:00 am
Categories: Events, Foundries, TSMC

Global Footprint

TSMC also covered manufacturing excellence. The TSMC “Trusted Foundry” tagline has many aspects to it, but manufacturing is a critical one. TSMC is the foundry capacity leader but there is a lot more to manufacturing as you will read here. Which brings us to the manufacturing accomplishments from the briefing:

To meet customers’ growing demand, TSMC has accelerated its fab expansion rate:
  • From 2017 to 2019, TSMC built around 2 phases of fabs on average per year.
  • From 2020 to 2023, the average will significantly increase to around 5
  • In the past two years, TSMC started the construction of 10 new phases in total, including 5 phases of wafer fabs in Taiwan, 2 phases of advanced packaging fabs in Taiwan, and 3 phases of wafer fabs overseas.
    • The overseas capacity of 28nm technology and below will be 3X larger in 2024 than it was in 2020.
    • In Taiwan, phases 5, 6, and 8 of Fab 18 in Tainan are the base of TSMC’s N3 volume production. In addition, TSMC is preparing new fabs, Fab 20 in Hsinchu and a new site in Taichung, for N2 production.
    • In the US, TSMC is planning for 2 fabs in Arizona.
  • The first fab for N4 has started tools move-in, and volume production will be in 2024.
  • The second fab is under construction now and is planned for N3 production.
  • Combined capacity for both fabs will reach 600K wafers per year.
    • In Japan, TSMC is building a fab in Kumamoto to provide foundry services for 16/12nm and 28nm family technologies to address strong global market demand for specialty technologies. Construction of this fab has begun and volume production will be in 2024.
    • In China, a new phase for 28nm technology started volume production in 2022.

TSMC’s leadership on advanced technology defect density (D0) and defective parts per million (DPPM) has demonstrated its manufacturing excellence.

    • The process complexity of N5 is much higher than N7, but N5’s yield improvement is even better than N7 at the same stage.
    • TSMC’s N3 technology has demonstrated industry-leading yield in high-volume production, and its D0 performance is already on par with N5 at the same stage.
      • TSMC’s N7 and N5 technologies have demonstrated industry-leading DPPM, including smartphones, computers, and cars, and TSMC is confident that N3 DPPM will catch up with N5 very soon.
3DFabric™ Manufacturing
  • By leveraging TSMC’s industry-leading 3DFabric™ manufacturing, customers can overcome the challenges of system-level design complexity and speed up product innovation.
  • CoWoS and InFO families have reached fairly high-level yields very soon after their volume productions.
  • The integrated yield of SoIC and advanced packaging will achieve the same level as the CoWoS and InFO families.
Green Manufacturing
    • To achieve the goal of net zero emissions by 2050, TSMC continues to evaluate and invest in all types of opportunities to reduce greenhouse gas emissions.
    • In 2022, TSMC’s direct greenhouse gas emissions have significantly dropped to 32% from 2010 levels.
    • This was achieved through reducing process gas consumption, replacing global warming potential gases, installing on-site abatement systems, and improving gas removal efficiency.

TSMC aims to double production energy efficiency for every process node after five years of volume production.

    • For N7 technology, the energy efficiency improved by 5X in the fifth year of its volume production.
    • For N5 technology, TSMC expects to see energy efficiency improvement by 5X by 2024.
    • TSMC has built an innovative chiller system with AI capabilities, which significantly contributed to improving cooling energy efficiency.

Last year, TSMC’s first water reclamation plant in southern Taiwan started supplying 5,000 metric tons of water per day. Today, it’s 20,000 tons per day.

    • By 2030, TSMC’s tap water consumption per unit of production will be reduced to 60% of 2020 level.
    • At TSMC Arizona, TSMC plans to build an industrial water reclamation plant to help the company reach near-zero liquid discharge. When completed, TSMC Arizona will be the greenest semiconductor manufacturing facility in the U.S.

After attending a handful of conferences in 2023 I must say that the TSMC Technical Symposium was by far the best. I don’t know the final attendance numbers but more than 1,600 people registered to attend this event. The exhibit hall was very busy and well stocked with food. Quite a few of the companies we work with on SemiWiki were exhibiting and I was told that for the cost it had by far the best ROI of semiconductor conferences.

The TSMC Technical Symposium will next go to Austin, Boston, Taiwan, Europe, Israel, China, and Japan. TSMC certainly knows how to build an ecosystem of customers, partners, and suppliers, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4