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Can TSMC Maintain Their Process Technology Lead

Can TSMC Maintain Their Process Technology Lead
by Scotten Jones on 04-29-2020 at 10:00 am
Categories: Foundries, Intel Foundry, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
10 Comments

TSMC Process Lead Slides 20200427 Page 1

Recently Seeking Alpha published an article “Taiwan Semiconductor Manufacturing Company Losing Its Process Leadership To Intel” and Dan Nenni (SemiWiki founder) asked me to take a look at the article and do my own analysis. This is a subject I have followed and published on for many years.

Before I dig into specific process density comparisons between companies, I wanted to clear up some misunderstandings about Gate All Around (GAA) and Complimentary FET (CFET) in the Seeking Alpha article.

Gate All Around (GAA)
Just as the industry switched from planar transistors to FinFETs, it has been known for some time that a transition from FinFETs to something else will eventually be required to enable continued shrinks. A FinFET has a gate on three sides providing improved electrostatic control of the devices channel compared to a planar transistor that has a gate on only one side. Improved electrostatic control provides lower channel leakage and enables shorter gate lengths. FinFETs also provide a 3D transistor structure with more effective channel width per unit area than planar transistors therefore providing better drive current per unit area.

It is well established that a type of GAA device – horizontal nanosheets (HNS) are the next step after FinFETs. If the nanosheets are very narrow you get nanowires and significantly improved electrostatics. The approximate limit of gate length for a FinFET is 16nm and for a horizontal nano wire (HNW) is 13nm, see figure 1. Shorter gate lengths are a component of shrinking Contacted Poly Pitch (CPP) and driving greater density.

Figure 1. Contacted Poly Pitch CPP Scaling Challenges.

Please note that in Figure 1, the 3.5nm TSMC HNW is just an example of how dimensions might stack up, we know they are doing FinFETs at 3nm.

The problem with a HNW is that the effective channel width is lower than it is for a FinFET in the same area. The development of HNS overcame this problem and can offer up to 1.26x the drive current of FinFETs in the same area although they sacrifice some electrostatic control to do it, see figure 2.

Figure 2. Logic Gate All Around (GAA).

Another advantage of HNS is the process is essentially a FinFET process with a few changes. This is not meant to understate the difficulty of the transition, the HNS specific steps are critical steps and the geometry of a HNS will make creating multiple threshold voltages difficult, but it is a logical evolution of FinFET technology. Designers are used to FinFETs with 4 and 5 threshold voltages available to maximize the power – performance trade off, going back to one or two threshold voltages would be a problem, this is still an area of intense HNS development and needs to be solved for wide adoption.

At the “3nm” node Samsung has announced a GAA HNS they call a Multibridge, TSMC on the other hand is continuing with FinFETs. Both technologies are viable options at 3nm and the real question should be who delivers the better process.

Complementary FETs (CFET)
In the Seeking Alpha article there is a comment about a CFET offering 6x the density of a 3 fin FinFET cell, that isn’t how it works and in fact the comparison doesn’t even make sense.

Logic designs are made up of standard cells, the height of a standard cell is given by metal 2 pitch (M2P) multiplied by the number of tracks. A recent trend is Design Technology Co Optimization (DTCO) were in order to maximize shrinks the number of tracks has been reduced at the same time as M2P. In a 7.5 track cell, it is typical to have 3 fins per transistor but as we have transition to 6 track cells available at 7nm from TSMC and 5nm from Samsung, the fins per transistor is reduced to 2 due to spacing constraints. In order to maintain drive-current the fins are typically taller and optimized in other ways. As the industry moves to 5 track cells, the fins per transistor will be further reduced to 1.

Figure 3. Standard Cell layouts

CFETs are currently being developed as a possible path to continue to scale beyond HNS. In a CFET an nFET and pFET are stacked on top of each other as HNS of different conductivity types. In theory CFETs can scale over time by simply stacking more and more layers and may even allow lithography requirements to be relaxed but there is a long list of technical challenges to overcome to realize even a 2 deck CFET. Also, due to interconnect requirements going from a HNS to a 2 Deck CFET is approximately a 1.4x to 1.6x density increase, not 2x as might be expected. For the same process node, a 2 deck CFET would likely offer a less that 2x density advantage over an optimized FinFET, not 6x as claimed in the Seeking Alpha article.

2019 Status
In 2019 the leading logic processes in production were Intel’s 10nm process, Samsung’s 7nm process and TSMC’s 7nm optical process (7FF). Figure 5 compares the three processes.

Figure 4. 2019 Processes.

In figure 4, M2P is the metal 2 pitch as previously described, tracks are the number of tracks and cell height is M2P x Tracks. CPP is the contacted poly pitch and SDB/DDB is whether the process has a single diffusion break or double diffusion break. The width of a standard cell is some number of CPPs depending on the cell type and then DDB adds additional space versus a SDB at the cell edge. The transistor density is a weighted average of transistor density based on a mix of NAND cells and Scanned Flip Flop cells in a 60%/40% weighting. In my opinion this is the best metric for comparing process density, it isn’t perfect, but it takes designs out of the equation. A lot of people look at an Intel Microprocessor designed for maximum performance and compare the transistor density to something like an Apple Cell Phone Process with a completely different design goal and that simply doesn’t provide a process to process comparison under the same conditions.

It should be noted here that Samsung has a 6nm process and TSMC has a 7FFP that both increase the transistor density to around 120MTx/mm2, In the interest of clarity I am focusing on the major nodes.

2020 Status
At the end of 2019, Samsung and TSMC both began risk production of 5nm processes and both processes are in production in 2020.

5nm is where TSMC really stakes out a density lead, TSMC’s 5nm process has a reported 1.84x density improvement versus 7nm whereas Samsung’s 5nm process is only a 1.33x density improvement. Figure 5 compares Intel’s 10nm process to Samsung and TSMC’s 5nm processes since 10nm is still Intel’s densest process in 2020.

Figure 5. 2020 Processes.

The values for Samsung in figure 5 are all numbers that Samsung has confirmed. The TSMC M2P is an incredible 28nm, a number we have heard rumored in the industry. The rest of the numbers are our estimates to hit the density improvement TSMC has disclosed.

Clearly TSMC has the process density lead at the end of 2020.

2021/2022
Now the situation gets fuzzier, Intel’s 7nm process is due to start ramping in 2021 with a 2.0x shrink. Samsung and TSMC are both due to begin 3nm risk starts in 2021. Assuming Intel hits their date, they may briefly have a production density advantage but Intel’s 14nm and 10nm process have both been several years late. With COVID 19 impacting the semiconductor industry in general and the US in particular, a 2021 production date for Intel may be even less likely.

Figure 6 compares 2021/2022 processes assuming that within plus or minus a quarter or two all three processes will be available, I believe this is a fair assumption. Intel has said their density will be 2.0x 10nm, TSMC on their 2020-Q1 conference call said 3nm will be 70% denser than 5nm so presumably 1.7x, Samsung has said 3nm reduce the die size by 35% relative to 5nm and that equates to a approximately 1.54x denisty.

In order to make Intel’s numbers work I am assuming an aggressive 26nm M2P with 6 tracks, an aggressive 47nm CPP for a FinFET and SDB.

For Samsung they have disclosed to SemiWiki a 32nm M2P for 4nm and I am assuming they maintain that for 3nm with a 6-track cell. For CPP with the change to a GAA HNS, they can achieve 40nm and SDB.

In the case of TSMC they are shrinking 1.7x off of a 5nm process that is a 1.84x shrink from 7nm and they are bumping against some physical limits. With them staying with a FinFET I don’t expect the CPP to be below 45nm for performance reasons and even with SDB they will have to have a very aggressive cell height reduction. By implementing a buried power rail (BPR) they can get to a 5-track cell, BPR is a new and difficult technology and then an M2P of 22nm is required. Frankly such a small M2P raises issues with lithography and line resistance and BPR is also aggressive so I think this process will be incredibly challenging but TSMC has an excellent track record of execution.

Figure 6 summarizes the 2021/2022 process picture.

Figure 6. 2021/2022 Processes.

Some key observations from figure 6.

  1. The individual numbers in figure 6 are our estimates and may need to be revised as we get more information, but the overall process densities match what the companies have said and should be correct.
  2. In spite of being the first to move to HNS, Samsung’s 3nm is the least dense of the three processes. The early move to HNS may make it easier for Samsung to shrink in the future but for their 3nm node isn’t providing the density advantage that you might expect from HNS.
  3. Yes Intel is doing a 2.0x shrink and TSMC only a 1.7x shrink, but TSMC is doing a 1.84x shrink from 7nm to 5nm and then a 1.7x shrink from 5nm to 3nm in roughly the same time frame that Intel is doing a 2.0x shrink from 10nm to 7nm. A 1.7x shrink on top of a 1.84x shrink is a huge accomplishment, not a disappointment.

What’s Next
Beyond 2021/2022 I expect Intel and TSMC to both adopt HNS and Samsung to produce a second generation HNS. This will likely be followed by CFETs around 2024/2025 from all three companies. All of these confirmed numbers and projections come from the IC Knowledge – Strategic Cost and Price Model. The Strategic Cost and Price Model is not only a company specific roadmap of logic and memory technologies into the mid to late 2020s, it is also a cost and price model that produces detailed cost projections as well as material and equipment requirements.

Interested readers can see more detail on the Strategic Cost and Price Model here.

Conclusion
TSMC took the process density lead this year with their 5nm process. Depending on the exact timing of Intel’s 7nm process versus TSMC 3nm Intel may briefly regain a process density lead but TSMC will quickly pass them with their 3nm process with over 300 million transistors per millimeter squared!

Also Read:

SPIE 2020 – ASML EUV and Inspection Update

SPIE 2020 – Applied Materials Material-Enabled Patterning

LithoVision – Economics in the 3D Era

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Tracing Technology’s Evolution with Patents

Tracing Technology’s Evolution with Patents
by Arabinda Das on 04-23-2020 at 10:00 am
Categories: FinFET, Foundries, TSMC
2 Comments

Figure 1

We live in an age of abundant information. There is a tremendous exchange of ideas crisscrossing the world enabling new innovative type of products to pop up daily. Therefore, in this era there is a greater need to understand competitive intelligence. Corporate companies today are interested in what other competitors are brewing in their R&D labs and in predicting what novel application is coming up in the market so as to determine the best possible plan of action to counterattack. Moreover, new players with radically innovative ideas are rapidly emerging as partly deduced from the massive shift in the patent filing scenario in the past years. For example, in 2000, the three countries which filed the most patents were US, Japan and Germany. But since 2019, China has become the largest patent filing country with World Intellectual Property Organization (WIPO), surpassing USA, Japan, and Germany. South Korea has also emerged as a top five patent producers [1]. Companies around the world are looking for a synthesis of information from this data deluge. They are relying on industry experts to provide the technological know-how but also on patent engineers or analysts to perform the analysis of intellectual property (IP) of a particular company and/or a whole industry. Their aim is to understand the activities of the main players as well as the fields in which they dominate. Creating such a detailed patent landscape is time-consuming and complex, however, the end result could provide deep insights into the technology and the market.

I have come across several thorough patent landscapes that have predicted emerging technologies quite accurately. However, I have found mixed results for semiconductor road maps especially those related to advanced logic devices. Specifically, some of the major technologically break-through concepts in advanced logic devices were not predicted in time by market analysts or industry experts. The most striking example is the introduction of finFET device (a tri-gate where the gate wraps around the silicon fin for better control of the channel) by Intel in 2012 for its i5-3550 processor which arrived completely as a surprise to the industry.

The story gets even more interesting after the introduction of finFET devices. Very quickly there were multiple reports that after 10 nm node finFET devices were not going to be extendable. Solutions were proposed in public forums like IEEE papers, IEDM and VLSI conferences. Needless to say, prior to the publication of every proposed solution in a public literature, multiple patents related to them were filed by all major device manufacturers. All the patents and non-patent literature could be grouped into two categories: new materials or new device architectures. They discussed either new materials with existing technologies or suggested radical solutions where new device architectures were fabricated with new materials. For example, some of the serious propositions with prototype data were the following device structures: ultra-thin-body (UTB) field-effect-transistor (FET) based on silicon-on-insulator (SOI), gate-all-around (GAA) involving nano-wires/nano-sheets stacked horizontally or vertically, tunneling FET (TFET), and stacked FET. Meanwhile the materials section mainly focused on silicon -germanium (SiGe) replacing the silicon (Si) channel for PMOS or using III-V compounds. However, today, we are at 7 nm node and slowly transitioning to 5 nm node and still moving forward with the original finFET configuration.

I wondered why these predictions were inaccurate and came to the following conclusions. Firstly, all these suggested devices in spite of their strengths had some serious concerns too. The ultra-thin-body (UTB) architecture gave the possibility of back biasing and also had low consumption of power. The initial wafer cost was high then. UTB is now not used but SOI based technology is currently widely prevalent in the market despite not being used in high speed processors. Similarly the GAA concepts provided better electrostatic control of the channel but required two materials which could be deposited one top of each other, each of them having a very different etch selectivity for the same etching chemistry. The onus on deposition and etching was high, which made the overall process flow very expensive. Vertical GAA FET devices which required major integration change as the wire-shaped channel regions were perpendicular to the substrate (implying that source and drain regions were not on the same plane) were especially hindered by their requirements. This implied additional process steps involving deposition and etching which would make the manufacturing of advanced logic devices even more expensive. Regarding TFET, there was the promise of attaining the sub-threshold slope limit of 55mV/dec, which could open new applications for low power computing. However, the band gap tunneling based TFET devices unfortunately lacked a robust drive current. Next, let us consider stacked FET devices. This idea had been floating since a long time in the technical forum. In this concept, transistors are stacked one on top of another. Either the transistors are made in separate wafers and bonded or they are fabricated directly on the lower layer of transistors. This requires good bonding techniques or proper controlling of the thermal budget for the top devices. Additionally, controlling the implant process could be difficult on the stacked layer. Back in 2012, the solutions were not ready. What about SiGe replacing Si? Most of the patents filed and literature submitted highlighted two possible scenarios both of which involved integration methods post fin formation. One requires growing SiGe on the side walls, while the other is recessing the fins between the isolation structures and growing SiGe on top of the fin (see figure 1). Both methods required at least additional mask sets and numerous process steps, which suggested that the end result would be expensive.

If you observe the track history of semiconductor manufacturers it becomes evident why none of these concepts ever made it into the mainstream. The continuous miniaturization or scaling of the devices has maintained the transistor count trend in accordance with Moore’s law even today [2]. The scaling is actually the shrinkage of all the dimensions of metal-oxide-semiconductor field effect transistor (MOSFET). Every time the semiconductor manufacturers were faced with process challenges or design difficulties due to scaling, they analyzed what is the smallest change that could be made in the  integration scheme in order to continue to use the existing tool set and process flows in the new technology node. They also had to consider whether new processes that were to be introduced could be extended to future nodes. The strategy is that in every technology node when some new process-integration step is introduced, the majority of other process steps are kept unaltered. The direct result of this strategy is that with each coming generation the process-flow becomes more stable and reliable.

This strategy of minimum change for every new generation is well exemplified in Intel’s processors. Intel’s 22 nm had the 5th generation of strained silicon engineering with raised source-drain having embedded graded SiGe for PMOS channel, and embedded Si for NMOS. Similarly, for channel and gate engineering, high-k with replacement metal gates were introduced in 45 nm node and was further improved in 32 nm node and finally implemented in 22 nm finFET structure. Intel has maintained the same finFET architecture up to 10 nm. Yet the device performance has improved and the transistors per unit area count has increased. In the case of TSMC it is equally impressive, TSMC introduced finFET device at 16 nm node in the iPhone 7 processor in 2016, and since has produced three new generations of finFET devices. According to the press release, it will also continue to use finFET devices in their 5 nm devices [3].

Needless to say the devil is in the details; detailed structural analyses are needed to understand the process evolution. Even though finFET configuration has remained as the workhorse since 2012, the evolution of the integration process flow and the design layout are impressive. In a broad sense, maximum changes and new process steps in advanced logic nodes take place near the gate structure, especially in the lowest interconnect structure closest to the gate. A glimpse of the process sophistication can be deduced from an old presentation of Intel, along with Mr. Dick James’ comments of Intel’s 10 nm process which includes cross-sections and detailed explanations about the changes in contact formation [4]. This article highlights how by changing the layout and the integration scheme the standard cell could be reduced and thus increase the number of transistors per unit area. A detailed survey of technology process of finFETs starting from 14 nm to 10 nm is well collected in a presentation from Siliconics [5]. This presentation is full of cross-sections and detailed explanations, and is quite a treasure trove. It elaborates some of the major innovations that have been introduced in finFET devices. For examples, it discusses, fin geometry and pitches, work function metal layers of NMOS and PMOS transistors, solid-source diffusion punch stop and its role, the introduction of novel materials in the lower interconnect structure, the structure of dummy gates at the fin end, post patterning fin removal, the coming of super vias that connect directly from metal 1 to the gate without the need of an intermediate metal 0 layer, the implementation of multi-stage contacts to the source-drain regions, the introduction of quadruple patterning for the front-end, and air-gaps in the back-end-of line. Figure 2 taken from this presentation shows a variety of contacts, which is only one of the novelties in finFET devices. And of course each of these process steps is backed by a family of patents. This illustrates the point that massive innovations were implemented on the same finFET device configuration.

Predicting near future technologies for semiconductor devices would require looking for patents that make incremental changes yet affect the cell area or the layout of interconnect structure closest to the gate. These patents would be able to make the miniaturization process without much disruption while still maintaining the integration flow, thus keeping the manufacturing cost low. Modern technology will accelerate the process of using patents to more effectively predict the near future technologies of semiconductor devices. Related ideas are already being tried out with the help of deep learning as in the case of Google which announced that it is experimenting with artificial intelligence to make more efficient chips. It is not looking for radical changes in device structures but rather optimizing what is available [6]. Semiconductor technology has never stopped innovating and will not stop surprising us and a thorough understanding of current process steps and their corresponding patents could be key to predicting what is still to come.

The ideas expressed in this article are solely the opinion of the author and do not represent the author’s employer or any other organization with which the author may be affiliated.

References

1/ https://twitter.com/WIPO/status/1247498105135566848

2/ https://www.semiconductor-digest.com/2020/03/10/transistor-count-trends-continue-to-track-with-moores-law/

3/ https://www.tsmc.com/english/dedicatedFoundry/technology/5nm.htm

4/ https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/10-nm-icf-fact-sheet.pdf

https://sst.semiconductor-digest.com/chipworks_real_chips_blog/2017/04/10/intel-unveils-more-10nm-details/

5/ https://nccavs-usergroups.avs.org/wp-content/uploads/JTG2018/JTG718-4-James-Siliconics.pdf

6/ https://www.zdnet.com/article/google-experiments-with-ai-to-design-its-in-house-computer-chips/

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TSMC COVID-19 and Double Digit Growth in 2020

TSMC COVID-19 and Double Digit Growth in 2020
by Daniel Nenni on 04-17-2020 at 10:00 am
Categories: Foundries, TSMC
3 Comments

Mark Liu CC Wei TSMC


TSMC has had an incredible run since its founding in 1987 which spans most of my 36 year semiconductor career. Even in these troubled times TSMC is a shining bellwether with double digit growth expectations while the semiconductor industry will be flat or slightly down. Let’s take a close look at the TSMC Q1 2020 conference call and see what else we can learn.

“On March 18, we found one employee who tested positive for COVID-19 and immediately began receiving appropriate care. Today, this employee has recovered, is out of the hospital and is staying at home for additional quarantine. We were able to suitably trace all the other individuals who were in contact. The neighboring employees have all tested negative, while all other employees who were in contact has entered and completed the 14-day self-quarantine and now back to work. As a result of the strict preventive measures taken by TSMC, we have not seen any disruption of our fab operations so far.”

This does not surprise me at all. Taiwan learned a very important lesson during the SARS outbreak in 2002. I remember traveling during this time and going through extra medical checks at the TPE airport. Taiwan installed medical imaging equipment that took our temperatures after we got off the planes. It is easy to remember since I had to remove my hat and got to see how big my brain is. It really is big, hat size XL.

One thing you can say about TSMC is that they have built their business on experience and humility, absolutely.

Dr. C.C. Wei:

“Looking ahead to the second half of this year. Due to the market uncertainty, we adopt a more conservative view as we expect COVID-19 to continue to bring some level of disruption to the end market demand. For the whole year of 2020, we now forecast the overall semiconductor market, excluding memory growth, to be flattish to slightly decline, while foundry industry growth is expected to be high single-digit to low-teens percentage.”

In my opinion we will see a hockey-stick-like semiconductor recovery in Q4 2020. Never before have we seen the entire world united in a common cause. Never before have we seen such worldwide compassion and cooperation. COVID-19 really is a globally uniting event and it could not have come at a better time in my opinion. The world will be a much safer and more productive place in 2021 and beyond, that is my heartfelt belief.

“Now let me talk about the progress and development of 5G and HPC. With the recent disruption from COVID-19, we now expect global smartphone units to decline high single digit year-over-year in 2020. However, 5G network deployment continues and OEMs continue to prepare to launch 5G phones. We maintain our forecast for mid-teens penetration rate for 5G smartphone of the total smartphone market in 2020.”

It is understandable that the edge devices will take a pause this year but remember we are in a data driven society. With the entire world sheltering in place the amount of data generated is increasing exponentially. SemiWiki traffic alone is up 30%. Our webinar series is breaking registration and attendance records. The world wide communications infrastructure is being upgraded like never before and that means semiconductor strength.

There has been a lot of fake news of late surrounding the TSMC process technology so let’s get this straight from the horse’s mouth (American idiom for the truth):

“Now let me talk about the ramp-up of N7, N7+ and the status of N6. In its third year of ramp, N7 continue to see very strong demand across a wide spectrum of products for mobile, HPC, IoT and automotive applications. Our N7+ is entering its second year of ramp using EUV lithography technology while paving the way for N6. Our N6 provides a clear migration path for next-wave N7 products, as the design rules are fully compatible with N7.”

“N6 has already entered its production and is on track for volume production before the end of this year. N6 will have one more EUV diode than N7+ and will further extend our 7-nanometer family well into the future. We expect our 7-nanometer family to continue to grow in its third year and reaffirm it will contribute more than 30% of our wafer revenue in 2020.”

“Now let me talk about our N5 status. N5 is already in volume production with good yield. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about 20% speed gain compared with N7. N5 will adopt EUV extensively. We expect a very fast and smooth ramp of N5 in the second half of this year driven by both mobile and HPC applications. We’ll reiterate 5-nanometer will contribute about 10% of our wafer revenue in 2020.”

“N5 is the foundry industry’s most advanced solution with best PPA. We observed a higher number of tapeouts, as compared with N7 at the same period of time. We will offer continuous enhancements to further improve the performance, power and density of our 5-nanometer technology solution into the future as well. Thus, we are confident that 5-nanometer will be another large and long-lasting node for TSMC.”

“Finally, I will talk about our N3 status. Our N3 technology development is on track, with risk production scheduled in 2021 and target volume production in second half of 2022. We have carefully evaluated all the different technology options for our N3 technology, and our decision is to continue to use FinFET transistor structure to deliver the best technology maturity, performance and costs.”

“Our N3 technology will be another full node stride from our N5, with about a 70% larger density gain, 10 to 15 speed gain and 25% to 30% power improvement as compared with N5. Our 3-nanometer technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced and will further extend our leadership position well into the future.”

If you have questions about this please post in the comments section and let the SemiWiki community of experts answer. Just say no to fake news….

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TSMC 32Mb Embedded STT-MRAM at ISSCC2020

TSMC 32Mb Embedded STT-MRAM at ISSCC2020
by Don Draper on 03-20-2020 at 6:00 am
Categories: Foundries, TSMC
5 Comments

Fig. 1. Cross section of the STT MRAM bit cell in BEOL metallization layers between M1 and M5.

32Mb Embedded STT-MRAM in ULL 22nm CMOS Achieves 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150C and High Immunity to Magnetic Field Interference presented at ISSCC2020

1.  Motivation for STT-MRAM in Ultra-Low-Leakage 22nm Process

TSMC’s embedded Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) offers significant advantages compared to Flash Non-Volatile Memory (NVM).  Flash requires 12 or more extra masks, is implemented in the silicon substrate and is page mode write alterable.  STT-MRAM on the other hand is implemented in the Back-End-Of-Line (BEOL) metallization as shown in Fig. 1, requires only 2-5 extra masks and is byte-alterable.

This implementation in TSMC’s 22nm Ultra-Low-Leakage (ULL) CMOS process has a very high read speed of 10ns, and read power of 0.8mA/MHz-bit. It has 100K cycle write endurance for 32Mb code and 1M cycle endurance for 1Mb data. It supports data retention for IR reflow at 260C of 90 seconds and 10 years data retention at 150C.  It is implemented in a  very small 1transistor-1resistor (1T1R) 0.046 mm2 bit cell and has a very low leakage current of 55mA at 25C for the 32Mb array equivalent to 1.7E-12A/bit when in Low Power Standby Mode (LPSM).  It utilizes a sensing scheme with per-sense amp trimming and 1T4R reference cell.

 

Fig. 1. Cross-section of the STT-MRAM bit cell in BEOL metallization layers between M1 and M5.

2.  1Transistor-1Resistor MRAM Bit Cell Operation and Array Structure
To reduce parasitic resistance on the write current path, a two-column common source line (CSL) array structure is employed as shown.

Fig. 2. Schematic of the 1T1R bit cell in the array of 512b column with the 2-column CSL

The word line is over-driven by a charge pump to provide sufficient switching current of hundred’s of mA for write operation requiring the unselected bit lines to be biased at a “write-inhibit voltage” (VINHIBIT) to prevent excess voltage stress on the access transistors of the  unselected columns of the selected row. To reduce bit line leakage of the access transistor on unselected word lines, the word line has a negative voltage bias (VNEG). The biasing of the array structure for reading, write-0 and write-1 is shown in Fig. 3.

Fig. 3. Cell array structure biasing for word lines and bit lines for read, write-0 and write-1 operations.

3.  Read Operation, Sense Amplifier and Word-Line Voltage System
For fast, low-energy wake-up from LPSM to enable high-speed read access, a fine-grained power gating circuit (one per 128 rows) with a two-step wakeup is used as shown in Fig. 4.  The power switch consists of two switches, one for the chip power supply VDD and the other for a regulated voltage from the Low Drop-Out (LDO) regulator supplying VREG.  The VDD switch is turned on first to pre-charge the WL driver’s power rail, then the VREG switch is turned on to raise the level to the targeted level, which achieves fast wake-up of <100ns while minimizing the transient current from VREG LDO.

Fig. 4. Fine-grained power gating circuit (one per 128 rows) with two-step wake-up.

The Tunnel Magnetoresistance Ratio (TMR) house curve shown in Fig. 5 is the ratio between the antiparallel resistance state Rap to the parallel resistance state Rp  as a function of voltage, showing lower TMR and smaller read window at higher temperatures.

Fig. 5 House curve of TMR showing the reduced window for read at 125C

The resistance distributions of the Rap and the Rp  states which, when including the bitline metal resistance and the access transistor resistance, determine the total read-path resistance showing the proportional reduction in the difference between the two states which the sense amp needs to measure to determine the bit value, as shown in Fig. 6.

Fig. 6. Distribution of resistance values for the anti-parallel Rap and the parallel Rp states and including the metal bit line and access transistor resistances showing the proportional reduction in the difference between the two states that needs to be detected by the sense amp.

To sense the resistance of the MTJ, the voltage across it during read must be clamped by transistors N1 and N2 to a low value to avoid read-disturb  and is trimmed to cancel the sense amp and reference current offset. The reference resistance is formed by the 1T4R configuration  R~(Rp +Rap)/2  + R1T as shown in Fig. 7.

Fig. 7.  Sense amp with trimming capability showing the read clamp voltage on transistors N1 and N2  to prevent read disturb. Reference R~(Rp +Rap)/2  + R1T

This configuration is able to achieve a read speed of less than 10ns at 125C as shown in the sensing timing diagram and shmoo plot Fig. 8.

Fig. 8.  Sensing timing diagram and read access shmoo plot at 125C.

4.  MRAM write operation
MRAM write of the parallel low resistance state, Rp and the higher resistance anti-parallel state Rap requires bi-directional write operation shown in Fig. 9. To write the Rap state to the Rp requires biasing the Bl to VPP, the WL to VREG_W0 and the SL to 0 to write the 0 state.    To write the 1 state, writing the Rp  state  to the Rap  state  requires current in the other direction, with the BL at  0, the SL at VPP and the WL at VREG_W1.

Fig. 9. Bi-directional Write for the parallel low resistance state, Rp and the higher resistance anti-parallel state Rap

For data retention during IR reflow at 260C for 90sec, an MTJ with a high energy barrier Eb is needed. This requires an increase in the MTJ switching current to hundreds of mA needed for reliable writing.  The write voltage is temperature compensated and a charge pump generates a positive voltage for selected cells and a negative voltage for unselected word lines to suppress bit line leakage at high temperatures. The write voltage system is shown in Fig. 10.

Fig. 10 Showing the over-drive of the WL and BL/SL by the charge pump and the temperature compensated write bias

Temperature compensation for write voltage is required for operation with a wide temperature range.  The write voltage shmoos from -40C to 125C are shown in Fig. 11 where the F/P blocks show fail at -40C while passing at 125C.

Fig. 11. Showing requirement for temperature compensation during write.

A BIST module with standard JTAG interface implements self-repair and self-trimming to facilitate test flow. The memory controller TMC implementing the Double Error Correction ECC (DECECC) shown in Fig. 12.

Fig. 12. BIST and Controller for self-repair and self-trimming during test and implementing DECECC.

The TMC implements the smart write algorithm which implements bias setup and verify/retry time for high write endurance (>1M cycles). It contains read-before-write to decide which bits need to be written and dynamic group-write to improve write throughput, multi-pulse write with write verify and optimizes write voltage for high endurance. The algorithm is shown in Fig. 13.

Fig. 13. Smart write algorithm showing dynamic group write and multi-pulse write with write verify.

5.  Reliability Data, Key Features and Die Photo

Fig. 14.  The write endurance test shows that the 32Mb chip access times and the read currents are stable before and after 100K -40C write cycles.

Fig. 15.  The write endurance bit error rate is less than 1 ppm at -40C after 1M cycles.

Fig. 16. The increased thermal stability barrier Eb  governing temperature dependence of data retention shows more than 10 years data retention at 150C, 1ppm.

Magnetic field interference is a potential concern in many applications for spin-based STT-MRAM. The solution is a 0.3mm thick magnetic shield deposited on the package as shown in Fig. 16 showing that in a field strength of 3500Oe of a commercial wireless charger for mobile devices the bit error rate of 100 hour exposure can be reduced from >1E6ppm to ~1ppm. Also, more than 10 years of data retention at 125C was shown at a magnetic field of 650 Oe.

Fig. 17. Sensitivity to a magnetic field of 3500 Oe reduced by a factor of 1E6.

Conclusions
The 22nm ULL 32Mb high-density MRAM has very low power, high read speed, very high data retention and endurance  suitable for a wide range of applications. With a cell size of only 0.0456mm 2 , it has a read speed of 10ns and a read power of 0.8 mA/MHz/b and in low-power standby mode (LPSB) it has leakage less than 55mA at 25C, equivalent to 1.7 E-12 A/bit leakage. For 32Mb code, it has an endurance of 100K cycles and for 1Mb data >1M cycles.  It has a capability of 90sec data retention under IR reflow at  260C and a long-term retention of > 10 years at 150C. The product spec is shown in Fig. 18 and die photo in Fig. 19.

Fig. 18.  Summary table of N22 MRAM specification and die photo.

Fig. 19.   32Mb high-density MRAM macro in the 22nm Ultra-Low-Leakage CMOS process.

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TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020

TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
by Don Draper on 03-06-2020 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

Fig. 1 Semiconductor Technology Application Evolution

Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their groundbreaking device developments such as High Mobility Channel (HMC) they are the leading implementers of Extreme Ultra-Violet (EUV) patterning to enable higher yield and shorter cycle time at this advanced node.

Semiconductor technology evolution has been driven by the application landscape which in the current phase of High-Performance Computing (HPC), Artificial Intelligence (AI) and 5G communication requires the highest performance with limited power dissipation as illustrated in Fig. 1.

Fig. 1 Semiconductor Technology Application Evolution

This technology was described by TSMC at IEDM 2019, where they described their 5 nm process which uses more than 10 Extreme Ultra-Violet (EUV) mask patterning steps replacing three or more immersion mask steps each and High Mobility Channel (HMC) technology for higher performance. This technology has been in risk production since April of 2019 and will be in full production 1H2020.

The implementation of this technology for the development of high- performance SRAM bit cells and arrays was described by Jonathan Chang, et al at ISSCC2020.

The quantizing of FinFET transistor sizing continues to be a major challenge and forces all transistors in the high-density 6T SRAM cell to use only a single fin. The design is optimized through Design-Technology Co- Optimization (DTCO) to give high performance and density as well as high yield and reliability. SRAM bit cell scaling for 2011 to 2019 is shown in Fig. 2.

Fig. 2. SRAM bit cell scaling is shown for 2011 to 2019.

It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement. Further area reduction utilizing Flying Bit Line (FBL) architecture is implemented for 5% area savings. The layout of the 5nm cell is shown in Fig. 3.

Fig. 3. Layout of the high-density 6T SRAM bit cell.

For power reduction, a key approach is lowering the minimum operating voltage Vmin of the SRAM array. The increased random threshold voltage variation in this latest technology limits Vmin which in turn limits the opportunities for power reduction. The SRAM voltage scaling trend is shown in Fig. 4, where the blue line indicates the Vmin without write assist and the red line indicates Vmin with write assist, showing great benefit of write assist with each generation. It will be observed that the Vmin from 7nm to 5nm shows very little improvement, indicating that further power reduction must be gotten from improvements in write assist generation circuits. This article will describe the major write assist methods to enable lower Vmin in operation, negative bit line (NBL) and Lower Cell VDD (LCV).

Fig. 4. SRAM cell voltage scaling trend without write assist (blue line) and
with write assist (red line).

The SRAM cell schematic is shown in Fig. 5 showing contention during write between the PU and pass-gate transistor PG. A stronger PU transistor would yield a higher read stability, but it degrades the write margin significantly and results in a contention write Vmin issue.

Fig. 5. SRAM cell schematic showing contention during write between the
PU and pass-gate transistor PG.

The first method to improve the write Vmin is to lower the bit line voltage during write, called Negative Bit Line or (NBL). This method has been employed for several years, using a MOS capacitor to generate a negative bias signal on the bit line, but this write assist circuitry results in area overhead. Furthermore, a fixed amount of MOS capacitance induces over boosted NBL level for short BL configuration and may led to dynamic power overhead in short bit lines, as shown in Fig. 6.

Fig. 6. Fixed amount of MOS capacitance induces over-boosted NBL level
for short BL configuration and may lead to dynamic power overhead
avoided by the metal cap NBL.

The overboost and the MOS capacitor area issues can be avoided by using a metal capacitor-coupled scheme based on coupled metal tracks laid out on top of the upper metal of the SRAM array. To avoid the overboost, the metal capacitor length can be modulated with the SRAM array bit line length, saving dynamic power. Furthermore, the coupled NBL level can also be adjusted to compensate the loss of write ability induced by BL IR drop on the far-side bit cell.

The NBL enable signal (NBLEN) in Fig. 7 drives one side of the metal capacitor C1 negative which couples a negative bias signal at the virtual

ground node NVSS which then passes through the write driver WD and column multiplex to the selected bit line.

Fig. 7. The NBL enable signal (NBLEN) couples the configurable metal
capacitor C1 to NVSS.

The NBL coupling level with different bit line configurations, Fig. 8, showing that the configurable metal capacitor C1 can track with bit line length so that the variation of the coupling NBL level with different Bit line length can be mitigated.

Fig. 8. NBL coupling level with different bit line configurations showing the
longer 256bit bitline (blue) having an extended NBL boosted level.

The second method of write assist is to Lower the Cell VDD, (LCV). The conventional techniques of LCV require a strong bias or an active-divider to adjust the column-wise bit cell power supply during write operation, but these techniques consume a huge amount of active power across operating time. Pulse Pull-down (PP) and Charge Sharing (CS) techniques are two alternative solutions but precise timing is difficult for PP, so CS is proposed using metal wire charge sharing capacitors on top of the array as shown in Fig. 9.

Fig. 9. Charge Sharing (CS) for Low Cell VDD (LCV) for write assist using
CS metal tracks on top of the SRAM array.

In write operation, the LCV enable signal (LCVEN) goes high, it turns off the pull low NMOS (N1) to isolate the charge sharing capacitor C1 from ground. A column is selected by COL[n:0] to turn the header P0 off and isolates the array virtual power rail CVDD[0] from true power VDDAI. Because the metal wire capacitance scales along with the size of the bit-cell array, it also benefits the SRAM compiler design and provides a relatively constant charge sharing voltage level with varied BL configurations. The charge sharing level is determined by metal capacitance ratio of CVDD and the charge sharing metal track. Fig. 10 shows three LCV-VDD ratios are implemented for 6%, 12% and 24%.

Fig. 10. Three LCV-VDD ratios are implemented for 6%, 12% and 24%.
With write assist turned off, Vmin is constrained by write failure. Measured
results with Write Assist in Fig. 11 show NBL improves Vmin by 300mV and 24% LCV improves Vmin independently by over 300mV.

Fig. 11. Measured results of (a) metal capacitor-boosted Write Assist
WAS-NBL scheme and (b) metal charge-sharing capacitor WAS-LCV
scheme.

Performance of the 5nm process is enhanced by the High Mobility Channel with ~18% drive current gain shown in Fig. 12. This technology was described in detail at IEDM2019.

Fig. 12. High Mobility Channel (HMC) performance gain of ~18%.
This performance gain is exemplified by the high-speed SRAM array for
L1 cache application achieving 4.1Ghz cycle time t 0.85V shown in the
shmoo plot in Fig. 13.

Fig. 13. Shmoo plot of the HD SRAM array for use as a high performance
L1 cache showing 4.1 GHz at 0.85V. The measured results are based on the 135 Mb test chip shown in Fig. 14.

Fig. 14. 135 Mb test chip in 5 nm HK-MK FinFET with High Mobility
Channel (HMC) and 0.021um 2 SRAM bit cell.

In summary, the detailed circuit design techniques described here enable the product developer to get the maximum advantage from this leading technology. An important device development approach is to do Design- Technology Co-optimization (DTCO) between product/circuit designers and process developers responsible for product yield and reliability.

ALSO READ: TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

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TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019
by Don Draper on 02-05-2020 at 10:00 am
Categories: Events, Foundries, TSMC
18 Comments

Diagram of BEOL metallization comparing EUV vs. immersion photolithography

Back in April, 2019, TSMC announced that they were introducing their 5 nm technology in risk production and now at IEDM 2019 they brought forth a detailed description of the process which has passed 1000 hour HTOL and will be in high volume production in 1H 2020.  This 5nm technology is a full node scaling from 7nm using smart scaling of major design rules (gate, fin and Mx/Vx pitches) for improved yield featuring an SRAM cell of 0.021um2 and a declining defect density D0 that is ahead of plan.

A primary reason for the success of the 5nm technology platform is the implementation of Extreme Ultra-Violet (EUV) photolithography.  Fully-fledged EUV replaces at least four times more immersion layers at cut, contact, via and metal line masking steps for faster cycle time, better reliability and yield. Total mask count in 5nm is several masks less than in the previous 7nm node.  Fig. 1 shows how one EUV mask replaced five immersion masks yet produces better patterning fidelity, shorter cycle time and fewer defects.

Fig. 1. Diagram of BEOL metallization comparing EUV vs. immersion photolithography showing how one EUV mask replaced five immersion patterning layers with better patterning fidelity, shorter cycle time and fewer defects.

FinFETs have been used in four generations from the 16nm node to 7nm, but performance as a function of channel mobility has been stagnant.  To address this, the High Mobility Channel (HMC) was implemented to increase performance.  The TEM in Fig. 2 shows the fully-strained HMC lattice constant interfaced with the Si lattice constant. The diffraction pattern confirmed HMC strain.

Fig. 2. Diagram showing finFET cross-section TEM showing fully-strained HMC lattice constant interfaced with the Si lattice constant.  The second plot shows higher leakage vs drive current of the silicon vs HMC transistors. The third plot shows the channel stress in GPa vs channel depth from the fin top to the fin bottom. The diffraction pattern shown confirms the HMC strain.

The HMC finFET has excellent Id-Vg characteristics as shown in Fig. 3 and produces ~18% more drive current than the Si finFET.  Figure-of-Merit (FOM) ring oscillator standby power also correlates well to transistor leakages.

Fig. 3. Chart showing drain current vs gate voltage (Id vs Vg) characteristics of the High Mobility Channel (HMC) transistors for different drain voltages.  The second plot shows the off-current ranges, Ioff-N and Ioff-P and the relative impact on standby current of the seven different Vt’s available in the technology. The currents in both diagrams are in logarithmic scale with one decade per division.  The Drain-Induced Barrier Lowering (DIBL) is 45mV and 35 mV and the swing is 69mV and 68mV for p-channel and n-channel transistors respectively.

This 5nm CMOS platform technology is a full node scaling from the 7nm process described in IEDM 2016. The availability of up to seven Vt’s for each transistor type, shown in Fig. 4, enables product design to meet the needs of power efficiency in mobile SoC as well as peak speed requirements of HPC.

Fig. 4. Chart of up to seven Vt’s available in N5 showing standby power in uW vs speed in GHz for N5 and N5 HPC compared to N7 to meet maximum power efficiency for mobile and peak speed in HPC.   eLVT offers 25% faster peak speed over 7nm.  Silicon data close to matching FOM ring speed vs stand-by power.

New HPC features are the extremely Low VT (eLVT) transistor with 25% faster peak speed over 7nm   and three-fin standard cells for an additional 10% performance increase. The technology is available for 3D chip stacking using hybrid bonding.   In addition to impressive density and performance gains relative to 7nm, the technology has achieved 1000 hour HTOL qualification with improved stress aging characteristics relative to the 7nm technology. The high-yielding SRAM and logic defect density D0 is ahead of plan. Technological achievements enabling this progress feature full-fledged implementation of EUV and high-mobility channel (HMC) finFETs.

This 5nm platform technology was designed and developed to meet objectives of PPACT(Power, Performance, Area, Cost and Time to Market). Design-Technology Co-Optimization (DTCO) is emphasized for smart scaling, avoiding brute-force scaling which would lead to drastically-increased process cost and yield impact.  Design features such as gate-contact-over-diffusion and unique diffusion termination along with EUV-based gate patterning enable SRAM size reduction and increased logic density.  The 5nm technology offers 15% faster speed at the same power or 30% power reduction at the same speed with 1.84x logic density of the 7nm node , as shown in Fig. 5.

Fig. 5. Plot comparing the speed in GHz vs. the core area in um2 of the N5 technology vs the previous N7. The 5nm technology offers 15% faster speed at the same power or 30% power reduction at the same speed with 1.84x logic density of the 7nm node.

Interconnect delay has a critical impact on product performance and with each generation the interconnect propagation delay has been  getting significantly worse.  Backend metal RC and via resistance is shown in Fig. 6 for generations from N28 to N5. The tightest pitch Mx RC and the Vx Rc are kept similar to the 7nm node by EUV patterning, innovative scaled barrier/liner ESL/ELK dielectrics and Cu reflow.

Fig. 6.  Charts of  normalized BEOL metallization RC product and via resistance vs nodes from N28 to N5 are shown. For the tightest metal pitch, MX RC and via resistance Vx Rc are kept similar to that of the previous 7nm node by EUV patterning, innovative scaled barrier/liner ESL/ELK dielectrics and Cu reflow.

SRAM density and performance/leakage are critical for mobile SoC and for HPC AI. Scaling of SRAM cells with more advanced nodes is becoming more difficult in feature size terms of F 2.  The offered High Current (HC) and the High Density (HD) SRAM cells with cell areas of 0.025um2 and 0.021 um2 respectively are the densest in the industry as shown in Fig. 7. Consistent high yield of the 256 Mb SRAM and logic test chips of >90% peak yield and ~80% average yield (without repair) has been achieved.

Fig. 7.  Chart of published SRAM cell size in um2 vs year of publication. The 5nm HD SRAM cell at 0.021 um2 is the densest offered in the industry.

The Ultra-low leakage ULHD can be used to reduce retention leakage for better power efficiency while higher-speed HSHD SRAM may be used as an alternative to HC SRAM cells to allow ~22% reduction in memory area as shown in Fig. 8.

Fig. 8.  Chart of standby leakage in pA at 0.4V  vs cell current in uA for ULHD, HSHD and standard HD SRAM cells. The Vout vs Vin butterfly curve plots of the 5nm HD SRAM cell  are shown at voltages  from 0.75V down to 0.3V.

The shmoo plot of the 256Mb 0.021 um2 HD SRAM cell with full read/write function is shown down to 0.4V in Fig. 9.

Fig. 9.  Shmoo plot showing Vout vs Vin from 1.0V down to 0.4V of the 256Mb SRAM based on the 5nm 0.021 um2 HD SRAM cell.

The frequency response shmoo plots of the GPU and CPU blocks in the high-yielding logic test chip are shown in Fig. 10.

Fig. 10. Shmoo plots of frequency in GHz vs. voltage for the GPU and CPU blocks respectively in the high yielding logic test chip in the 5nm qualification vehicle.

The 256Mb HD/HC SRAM and logic test chip passed 1000 hour HTOL qualification. The SRAM Vmin showed a negligible shift at 168 hours and passed the 1000 hour HTOL with ~51mV margin as shown in Fig. 11.

Fit. 11.  Plots of log-normal distribution vs Vmin in mV at 168 hours HTOL showing negligible Vmin shift and at 1000 hours HTOL, passing 1000 hours with 51mV margin.

Stress aging data at 0.96 V and 125C on the 5nm FOM ring oscillator made with the High Mobility Channel finFETs shown in Fig. 12 with improved aging relative to the 7nm node.

Fig. 12. Plot showing T50% lifetime(years) vs. stress voltage Vstr of aging study at 125C of N5 HMC finFET ring oscillators and N7 silicon finFET ring oscillators showing improved aging at the 5nm node relative to that at 7nm.

Another important feature for HPC is the metal-insulator-metal (MiM) capacitor formed in the upper layers of the BEOL metallization.  The 5nm node MiM has 4x higher capacitance density than the typical HD-MiM and produces ~4.2% faster Fmax by minimizing transient drooping voltage and achieved ~20mV Vmin reduction in a CPU test chip.

HPC critically depends on high-speed IOs especially SERDES.  By successfully optimizing finFET driving strength and capacitance/resistance with special high-speed devices, PAM-4 SERDES transmitter speed of 112 Gb/s at 0.78 pJ/bit and 130 Gb/s at 0.96pJ/b power dissipation as shown in Fig. 13.

Fig. 13. Plots showing signal characteristics of voltage out in mV vs time in ps of 112 Gb/s and 130Gb/s data transmission in SERDES PAM-4 with 0.78pJ/b and 0.96pJ/b respectively.

In conclusion, TSMC has presented a very competitive technology platform, establishing itself as the leader in best-in-class highest density logic technologies.  Volume production in 1H 2020 will enable leading edge products in advanced SoC for mobile, especially 5G, as well as HPC applications for AI, datacenter and blockchain products which increasingly need high performance with best power efficiency.

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ASML “A Swing to Memory Looms” Nice performance while awaiting Memory bounce

ASML “A Swing to Memory Looms” Nice performance while awaiting Memory bounce
by Robert Maire on 01-24-2020 at 6:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

ASML 2020 Logic Memory
  • Good Q4 & 2019 despite weak memory
  • 2020 will be up year but memory an unknown
  • EUV ramp is on track – no China or memory impact
ASML reports an “in line” Q4 despite industry weak 2019

ASML reported sales of 4B Euros and a nice gross margin of 48% resulting in 2.70 Euros per share in earnings.  Orders came in at 2.4B Euros with roughly 80% coming from logic. Despite 2019 being a down year for semiconductor equipment as a whole, ASML managed to have 8% growth during 2019 as spending in the industry shifted back towards lithography purchases,  We expect this trend of enhanced litho spending to hold true in 2020 as the industry continues its EUV adoption.

Logic (TSMC) remains the biggest driver at roughly 80%
It is interesting to note that ASML was able to keep up its growth despite the fact that memory spend went from the majority of sales in 2019 down to roughly 20% of sales at the close of the year. Despite this huge shift in end market demand the company has maintained good growth.

It obviously helps a lot to have strong backlog and a strong order book to be able to more efficiently manage the ebbs and flows of customer mix as 2019 was not an ebb and flow but more of a stampede away from memory to logic/foundry. It also helps that EUV is obviously focused on foundry/logic so the stampede was to ASML’s benefit as well.

“Focus” changes from making EUV work to making more EUV…..
It is also very clear that now that we are well over the acceptance and HVM hurdle of EUV, attention is now turning to turning out more systems faster. Getting down cycle times and getting the supply chain cranked up while still hard is not as hard as working out the kinks has been over the last few years.

2020 looks to be about 35 EUV tools with an eye towards 50 in 2021.  These seem like reasonable, “doable” targets.  We don’t think we need a full blown memory recovery to get to this years goal of 35 and memory will likely recover soon enough to support a 2021 goal of 50.

There is still a lot of work to be done on high NA but less critical than the original work as high NA is an improvement rather than wholesale change.

Multibeam delay helps KLA
One of the few negative points raised, although minor, was the delay of multibeam.  While not totally unexpected given the complexity, it does give KLA a bit of time to work on their products and counter measures.

In our view now that the war has been won on EUV, ASML can and should shift some more focus and spend to metrology & yield related issues and tools and products as it will also support the infrastructure for EUV going forward.

Memory still an unknown
It was clear from the call and clear in our view that the recovery of the memory industry is very much unclear. While NAND will no doubt recover first and DRAM some time later, the company gave no indication other than “just hoping” that memory recovers.  There was no evidence given nor implied of improved order activity or any other indication of memory spend coming back any time soon.

Like the rest of the industry, the key to a strong up cycle is memory along with foundry/logic both working at the same time….we remain with foundry/logic at roughly 80% of business with memory barely plodding along. This is obviously more of a negative for players like Lam who are much more memory centric.  Even though business at Lam and Applied has picked up of late, its not like the rip roaring memory love fest.

China is a non-issue
There remains a lot of discussion in the press about poor ASML being the ping pong ball in a game between China and the US.  So far we see zero impact from any sales restriction to China.  We expect no near term ill effects on ASML and the real issues and impact are more political than financial.  Though ASML may not be happy to be a pawn it hasn’t impacted their profitability or overall sales. We think there is a higher level of risk of the embargo spreading to US equipment companies that would see more financial impact.

The stocks
Given that the quarter was just in line with no surprises, we expect little movement in an already fully priced stock. There was also nothing surprising nor significantly impactful on other stocks that would drive the group one way or another.  The lack of any sign of memory recovery is a little bit disappointing for the group that has seen its shares on a tear despite the weakness.

All in all no impact and we are not motivated to run out and chase stocks that have already run up nor are we tempted to short stocks that have such unusual support.

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TSMC Q4 2019 “2020 Bellwether” Conference Call Summary

TSMC Q4 2019 “2020 Bellwether” Conference Call Summary
by Daniel Nenni on 01-20-2020 at 6:00 am
Categories: Foundries, TSMC
17 Comments

TSMC Manufacturing Excellence

After returning from a week in Southern China I found the TSMC Q4 2019 conference call even more interesting. In China they are preparing for the New Year’s Celebration so everything is very festive but what struck me hardest was the massive investment in infrastructure and security. Semiconductors are of course a big part of that thus the urgent need for China to be semiconductor-self-sufficient, absolutely.

TSMC of course is a valued partner of China and will benefit the most from China’s continued semiconductor boom. If you read between the lines of the TSMC Q4 conference call you will see it more clearly. First let’s look at the technology parts of the prepared statement:

“16-nanometer and below, accounted for 56% of wafer revenue, up from 51% in the third quarter. On a full year basis, 7-nanometer contribution increased from 9% in 2018 to 27% of wafer revenue in 2019. 10-nanometer was 3% and 16-nanometer was 20%. Advanced technologies accounted for 50% of total wafer revenue, up from 41% in 2018.”

It is interesting to note that TSMC 20nm and 16nm shared fabs where 20nm was the sacrificial lamb and 16nm is the cash cow. It was the same with 10nm and 7nm (cash cow). So, what is going to happen now that TSMC is moving 7nm customers to 6nm and 5nm is ramping up this year? Will TSMC break the cycle and have two cash cows in a row? From what I have been told 6nm is an EXCELLENT process and will be VERY competitive on price / performance with both TSMC and Samsung 5nm. In fact, my guess is that TSMC 6nm will even outperform Intel 10nm on density, yield, and most certainly cost.

“Now let’s take a look at revenue contribution by platform…. On a full year basis, smartphone and IoT led the growth with 12% and 33%, respectively, while HPC, automotive and DCE decreased 8%, 7% and 8%, respectively… Overall, smartphone accounted for 49% of our 2019 revenue; HPC, 30%; and IoT, 8%.”

Remember, in 2019 China is second in TSMC revenue (20%) behind the US (60%) but well in front of the other parts of the world and China revenue is on the rise. My guess is that China will be 25% of TSMC’s revenue in 2020 further out pacing Japan, Korea, Taiwan, and the EU, who are all in single digits.

The TSMC smartphone and IoT surge are a very good reflection of the China market.

Samsung is being pushed out of china leaving Apple as the only foreign smartphone supplier in the top 5. Huawei is dominating and Huawei and TSMC go together like peanut butter and jelly. In order to compete the other China smartphone suppliers are forced to follow Huawei into the TSMC ecosystem so it is all about TSMC.

IoT is the interesting one. The number one IoT driver in China is security (cameras) which are EVERYWHERE and backed by AI. 5G is a national priority in China and will increase the abilities of AI on the edge.

For example, in the US we have license plate readers so our local police can identify and recover stolen cars and the criminals that are driving them. The next level is facial recognition where law enforcement can identify known criminals and recover them. China is already at that next level, semiconductors and AI are everywhere and there is no stopping it no matter how you feel about privacy.

“We raised our 2019 CapEx guidance by $4 billion to $14 billion to $15 billion, and we ended up spending $14.9 billion. Our 2020 capital budget is expected to be between $15 billion and $16 billion. Out of the $15 billion to $16 billion CapEx for 2020, about 80% of the capital budget will be allocated for advanced process technologies including 3, 5 and 7-nanometers, about 10% will be spent for advanced packaging and mask-making and about 10% for specialty technologies.”

As I mentioned before, TSMC won the 7nm, 6nm, and 5nm popular vote so do not be surprised if CapEx is again raised and we have another hockey stick of growth in Q4.

“For the full year of 2020, we forecast the overall semiconductor market growth excluding memory to be 8%, while foundry industry growth is forecast to be about 17%. For TSMC, we are confident we can outperform the foundry revenue growth by several percentage points in U.S. dollar term.”

Now that ‘s what I’m talking about… 20% growth. It really is satisfying when hard work pays off.

“Now allow me to talk about our N5 volume production. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about a 20% speed gain compared with 7-nanometer. N5 will adopt EUV extensively and is well on track for volume production in first half this year and with good yield.”

“Finally, I’ll talk about our N3 status. We are working with customers on N3’s design, and the technology development progress is going well. We have many technology options in development and we carefully evaluate all the different approaches. Our decision is based on technology, maturity, performance and cost… We will announce more details about our N3 technology at our TSMC North America Technology Symposium on April 29.“

TSMC N3 will again be FinFET based. We can talk more about this after the Symposium. The Q&A was pretty lame this time but here is the best answer:

“But I can just tell you that whatever you read on the newspaper is not true…”

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The Tech Week that was January 13-17 2020

The Tech Week that was January 13-17 2020
by Mark Dyson on 01-19-2020 at 10:00 am
Categories: China, TSMC

Semiconductor Weekly Summary 1

In a week where the “phase 1” trade deal between US and China was finally signed, here is all the key news from the semiconductor and technology sector around the world.

After 2 years of an ever increasing trade war, the US and China have signed the so called Phase 1 deal aimed at reducing trade frictions.

Just as important as what is in the phase 1 deal are the items that are left out and are the major items to negotiated for the next phase. This BBC article reviews the major items missing which include the issue of China subsidies to companies in of support it’s “Made in China 2025” policy. Also excluded is the ban on Huawei and further reductions in tariffs that still remain. Let’s hope that progress is made on these more difficult items soon.

According to Gartner, last year Intel regained the number 1 slot for semiconductor companies based on global revenue in 2019 as Samsung dropped to number 2 due to the decline in memory prices and sales in 2019. Overall Global semiconductor revenue dropped 11.9% in 2019 compared to a year ago according to Gartner.

2020 is starting off with a brighter forecast for the year. Semiconductor analyst company Future Horizons is predicting that the global semiconductor market will increase to US$451billion in 2020, this is a 10.2% increase compared to 2019.

This optimism is backed up by initial trade data from Korea, where Korean semiconductor exports rose 12% in the first 10 days of 2020 in a sign that the industry is recovering from the negative effects of the trade war. This is the first time the figures have shown growth since October 2018.

TSMC expects to post revenues of between US$10.2 billion and US$10.3 billion in the first quarter of 2020, representing a 1.4% sequential decrease, but up a massive 44% on a year ago. TSMC also set its capex target this year at between US$15 ~16 billion, up from the US$14.9 billion allocated in 2019 with the majority of capex to be spent on advanced process nodes including 7nm, 5nm and 3nm.  TSMC’s Q4 revenue increased to US$10.4bn, up 10.6% sequentially of which 7nm chip shipments accounted for 35% of its total wafer revenues, up from 27% in the prior quarter. Advanced technologies, defined as 16nm and below, accounted for 56% of TSMC’s total wafer sales. In Q4 2019 smartphone revenues accounted for 53% of TSMC’s total wafer revenues, followed by the HPC segment with 29%, IoT with 8%, automotive 4% and digital consumer electronics 3%. In terms of markets, North America remained TSMC’s largest market with a 59% revenue share in Q4 whilst China accounted for 22%. This is up 9% compared to the same period in 2018. With business booming, according to Digitimes, TSMC 7nm process lead time remains at about six months, with tight supply expected to last through 2020

Also according to Digitimes, ASE is rumoured to be supplying to Apple antennas needed for mmWave 5G iPhones and iPad.

Elsewhere AMS has said it is confident it will get shareholder backing for it’s rights issue at it’s EGM on 24th January. The rights issue to raise US$1.84billion will help to partially refinance the US$4.42billion loan AMS took to acquire it’s 59.9% share of Osram.

With the expected recovery of the automotive market and it’s strong demand for SiC products, STMicroelectronics has signed a US$120million multi year supply deal for 150mm Silicon Carbide (SiC) wafers from SiCrystal AG which is part of the ROHM group. The deal adds extra SiC wafer capacity on top of existing deals STM has signed last year with other suppliers like Cree where it signed a multiyear US$250million supply deal and Norstel AB where it has acquired a majority stake in the company.

As a follow to a story last week, where the US put pressure on the Netherlands and ASML to not ship the latest EUV tool to China, the Chinese ambassador is quoted as saying that trade relations between China and the Netherlands would be damaged if ASML is prevented from selling the latest tools to China.

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Samsung spend is up but can it offest TSMC slowing?

Samsung spend is up but can it offest TSMC slowing?
by Robert Maire on 01-17-2020 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

TSMC Wafer

Samsung is warming up and spending again
Samsung gave its preliminary report for Q4 and it was well better than prior muted expectations. It doesn’t take long for Samsung’s business units to respond to business trends in either direction and we have already heard of increased spending plans on the part of Samsung.

Samsung has not been shy about spending and has even spent to excess as 2018 bore out.  Samsung is equally not shy about cutting spending when the industry slows. We have heard that Samsung has already started to spend even though the recovery in memory is still in early stages and DRAM is well behind NAND in terms of a recovery.

Obviously this is the Wayne Gretzky philosophy of “skate to where the puck is going, not where it has been”. Samsung is trying to get out in front of an expected memory uptick.

This is despite the fact that we have a ton of excess capacity in idled tools sitting around waiting to be turned back on which could easily satisfy increasing demand.

We think that part of Samsung’s spend is more focused on technology rather than pure capacity spend. Samsung has always tried to best its competitors by staying ahead of the cost/technology curve and one way to lead the way out of the memory slow down would be to have an ability to make money at pricing levels that competitors lose money at.

We certainly don’t expect the “drunken sailor” level of spend that Samsung exhibited in 2018 but rather more focused and cautious spend with a technology leaning.

Will Samsung’s spend offset an eventual TSMC decline? As we have previously mentioned, many times, TSMC is a “seasonal” spender focused on getting to the next node in time for Apple’s fall launch of new Iphones. This means that new tools an technology gets ordered and shipped in Q4 and Q1 to iron out the process in Q2 and ramp production in Q3 for the fall launch. We are currently in the midst of a big seasonal spend cycle for TSMC getting its 5NM act together. It is TSMC’s Q4 spend hockey stick that has gotten the equipment industry off the bottom of the cycle.

But all good things come to an end in this most cyclical of industries and TSMC’s spend will likely slow a bit after Q1 as it focuses its efforts on ramping up all that shiny new equipment for 5NM. The real question is will Samsung’s spending ramp offset the expected slowing of TSMC?  Probably yes…

We also expect a bit of share shift as memory based spend is obviously very different from logic/foundry spend.

BIS – Little known government agency may prove impactfull

Most people don’t know who or what BIS is.  It is a government agency whose acronym BIS stands for “Bureau of Industry & Security”.
With the recent revelation about behind the scenes US pressure on ASML it is clear the government is using an old tool to combat China in the semiconductor industry and that is “national security”.
Its clear that the trade deal has little to no IP protection in it so other means will have to be used to limit the technology flow.
We have suggested that we will likely see more involvement from the government in the form of export licenses/export controls and other methods that are not tariff based.
The mission statement of BIS- “Advance U.S. national security, foreign policy, and economic objectives by ensuring an effective export control and treaty compliance system and promoting continued U.S. strategic technology leadership.”- seems tailor made to be an alternative method to achieve goals that the trade deal didn’t.
We expect to hear more from companies over the next few quarters as the government gets more involved in the regulatory side of trade with China, especially, obviously, in tech.
With think ASML is both the tip of the iceberg and beginning of new phase of government involvement.
While we don’t expect an embargo, we could easily see more scrutiny, more export license issues, denial of export licenses or delays that may impact tech exports to China without an “overt” action.

What will companies report about Q4?

We think companies will generally be more positive. Reports of end product sales have been good. CES 2020 has been very positive and trade concerns have fallen by the wayside.
Memory is getting better. Tech stocks are doing great. Everything is happy.  This is all despite the fact that we are going into a seasonally weak Q1.
In general, companies are not likely to “fight the tape” and will likely talk about the improving environment going forward, probably more so because perceived potential risks are reduced.
2019 wasn’t as bad as it otherwise could have been
At one point, chip equipment companies were looking at a 20% down year versus 2017/18 given memory’s cliff dive. TSMC coming through at the end of the year looks to have limited the downside to a lot less, perhaps on down 10% or so.
The downturn lasted about 4 to 5 quarters spanning the second half of 2018 and first 3 quarters or so of 2019. The downturn spanning over two fiscal years rather than focused in one year has mitigated the absolute differential between peak and trough revenues.
Early reports great – Ichor is Punxsutawney Phil that throws no shade
Ichor, one of our favorite sub suppliers to the industry, just pre-announced a great Q4 and an excellent Q1 guide. This obviously bodes very well for both Lam and Applied the two biggest customers of Ichor.
Its not hard to extrapolate that Lam and Applied should have equally great reports – driven by both TSMC and the start of Samsung spend.
Ichor, being a sub-supplier in a cyclical industry is obviously highly levered to the cyclicality and will see even more leverage to the upside than their customers.
The company management has done a great job of acquisitions throughout the cycle and will likely see full benefit in the coming upcycle.  It also takes keen management to navigate the downcycle as well as Ichor has, and they have down a great job managing costs and Ichor is clearly a harbinger of good things coming to the industry.
The stocks
Lam and Applied (and of course Ichor) could easily be bought from the Ichor news.  We would also suggest MKS and AEIS as well as UCTT. Right now the news out of Q4 wiil be very good with Q1 outlook equally good so we see reduced downside in the near term for most of the stocks.