In early September of 2016 I published an article “The 2016 Leading Edge Semiconductor Landscape” that proved to be very popular with many views, comments and reposting’s. Since I wrote that article a lot of new data has become available enabling some projections to be replaced by actual values and new analysis and projections to be made.
The semiconductor industry has decades of history describing processes based on nodes but recently “nodes’ have become more marketing hype than reality. In my original article, I used a formula developed by ASML to convert process pitches into a standard node that applies the same definition to all processes providing a consistent method of node naming. The ASML formula is based on an analysis of 51 data points spanning the 130nm through 3nm nodes. Examining the ASML data plot it appears that as many as 14 of the data points may be 7nm, 5nm and 3nm projections. I decided to look at my own data and see how many data points I have from 130nm through 7nm that I can analyze to develop a formula using the same type of analysis. I was able to build a database of 55 data points representing 12 companies and only 2 of the 55 data points are projected – 7nm for GLOBALFOUNDRIES (GF) and Samsung as described below. I also decided to use contacted poly pitch (CPP) multiplied by minimum metal pitch (MMP) instead of half pitches as ASML did because I find it more convenient. The resulting data plot is shown in slide 1.
Slide 1: .
The resulting formula is:
Standard Node = 0.0427 (CPP x MMP)[SUP]0.6929[/SUP]
The R[SUP]2[/SUP] value for the analysis is 0.9912 indicating an excellent fit and I will use this formula for the comparisons presented later in this article.
The CPP and MMP for 10nm processes are now known and some 7nm pitches are also known. To analyze these pitches and project other 7nm and 5nm pitches it is useful to understand the limits of various lithography techniques. These lithography limits represent “cliffs’ that if passed result in significant changes in lithography costs. The approximate logic pitch limits for selected lithography techniques are presented in the following table:
[TABLE] class=”cms_table_grid” style=”width: 300px”
| class=”cms_table_grid_td” style=”text-align: center” | Technique
| class=”cms_table_grid_td” style=”text-align: center” | Minimum pitch (nm)
| class=”cms_table_grid_td” style=”text-align: center” | Single ArFi exposure
| class=”cms_table_grid_td” style=”text-align: center” | 80
| class=”cms_table_grid_td” style=”text-align: center” | Self-aligned double patterning (SADP)
| class=”cms_table_grid_td” style=”text-align: center” | 40
| class=”cms_table_grid_td” style=”text-align: center” | 2D EUV exposure
| class=”cms_table_grid_td” style=”text-align: center” | 36
| class=”cms_table_grid_td” style=”text-align: center” | 1D EUV exposure
| class=”cms_table_grid_td” style=”text-align: center” | 26
| class=”cms_table_grid_td” style=”text-align: center” | Self-aligned quadruple patterning (SAQP)
| class=”cms_table_grid_td” style=”text-align: center” | 20
The pitch limits presented in the table are based on limits published by IMEC. Moving from a single ArFi exposure to SADP and from SADP to SAQP increases process complexity and cost. Moving to EUV techniques from SAQP with multiple block masks should result in a cost savings once EUV is production ready.
Other considerations when developing pitch limits and lithography strategies for advanced processes relate to differences in the Front End Of Line (FEOL) and Back End Of Line (BEOL). In the FEOL fin and poly gate definition are single mask level – line/space patterns that are very sensitive to line smoothness. In the BEOL there are typically ~5 – 1x metal levels and line smoothness is less critical. We will assume that even when EUV is available SADP or SAQP will continue to be used in the FEOL due to superior line smoothness that results. In the BEOL where multiple metal levels may require SAQP with multiple block masks, EUV single exposures may provide significant cost savings.
7nm and 5nm
Intel has announced a 54nm CPP for their 10nm process and I have heard from multiple sources that their MMP is 40nm. For their 22nm process Intel used an 80nm MMP to avoid multi-patterning and apparently at 10nm they have decided to use a 40nm MMP to avoid SAQP. TSMC has announced their 7nm MMP is 40nm, also apparently deciding to avoid SAQP. Switching from SADP to SAQP for 4 to 5 metal layers would have a significant impact on cost. I have also heard from multiple sources that TSMC’s 7nm CPP is 54nm making TSMC’s 7nm CPP x MMP identical to Intel’s 10nm CPP x MMP.
Authors note: in my original analysis, I had projected tighter pitches for TSMC at 7nm based on their announced 10nm to 7nm 1.63x density improvement. However, I have now learned that part of the 1.63x density improvement is due to a move from a 7.5 track minimum cell size at 10nm to a 6 track minimum cell size at 7nm.
At IEDM in December IBM presented a paper based on work done by the GF, IBM, Samsung – Global Alliance. In that paper a 7nm process was presented with a 48nm/44nm CPP and 36nm MMP. GF and Samsung each have their own internal 7nm development programs underway and one key question is whether the IEDM paper represents the pitches that either or both company will use. Before examining that issue, it is useful to also examine what each company has said about their approach to lithography at 7nm. GF has said that their 7nm will be based on optical lithography and be designed around what can be achieved by that technique, Samsung on the other hand has said their 7nm process will use EUV. We are therefore projecting that GF will have a 40nm MMP to avoid SAQP and that Samsung will have a 36nm MMP (the 2D limit of EUV).
The only company to make a public statement about their 5nm plans that I am aware of is TSMC who have said they will achieve a 1.85x density improvement for 5nm versus their 7nm process. TSMC is also expected to introduce EUV at 5nm. If TSMC utilizes a 40nm CPP – the minimum pitch achievable by SADP, and a 29nm MMP – achievable by single EUV exposure assuming a 1D pattern, the resulting CPP x MMP is 1.85 the density of their 7nm process. We are assuming that at 10nm Intel will have the same pitches as TSMC’s 5nm process
For GF and Samsung we are assuming they will continue to be more aggressive on pitches than TSMC with a 40nm CPP – the minimum pitch for SADP and a 26nm MMP – the minimum pitch for 1D single exposure EUV.
Lacking any guidance on 7nm/5nm density from Intel and GF/Samsung their pitches are more speculative than TSMC’s, but we believe the values presented are reasonable.
Slide 2 presents our projected CPP versus MMP for each company compared to the lithography “cliffs”.
Standard Node Versus Time
We can now project standard node versus time for each company. We expect to see 7nm from TSMC late 2017 and 5nm late 2019. Intel 10nm was expected late 2017 but we are now hearing they have worked out their yield issues and are transferring the process to Israel, we therefore expect to see 10nm from Intel in early 2017. Intel is now on a roughly 2-1/2 year cadence for processes so we expect 7nm from Intel in 2020. We expect 7nm from GF in early 2018 and 5nm in 2020. For Samsung 7nm with EUV is expected late 2018 and we also expect 5nm from them in 2020.
The resulting standard node versus time projection for the companies is shown in slide 3.
Samsung and TSMC have taken the lead from Intel for process density with 10nm processes introduced this year. We expect that Intel will regain the lead in early 2017 with their 10nm process. We expect GF to then take the process density lead in early 2018 with their optical based 7nm process followed by Samsung taking the lead in late 2018 with their EUV based 7nm process.
Also read:IEDM 2016 – 7nm Shootout