Daniel Nenni recently blogged about Intel’s claims of industry leading process density that were made at their analysts meeting. It isn’t clear to me why Intel makes this such a big focus at the analysts meetings, they really don’t compete with the foundries much but this seems to be a big deal to them. I thought it would be interesting to take a detailed look at Intel’s 14nm process and contrast it to Samsung’s 14nm process and put some of these claims in perspective. I picked Samsung because Samsung has the densest 14nm foundry process.
Dan’s blog is available here.
With 14nm parts now out in the market from both Intel and Samsung a lot is known about both processes, in fact I believe I have a good detailed understanding of both processes. In this article I am going to focus on the back end of line (BEOL) because I believe it really illustrates the differences in approaches.
Samsung 14LPE process
Samsung’s 14LPE process is a foundry process and as such it has to accommodate a wide variety of customer needs. The process offers 4 levels of minimum pitch metal (64nm). The minimum pitch metal layers at 64nm are below the single patterning limit of ~80nm and therefore require multi-patterning. Samsung has chosen to use litho-etch-litho-etch (LE2) where the pattern is broken up into two masks that are exposed and etched separately. There are advantage and disadvantages to LE2 as a multi patterning approach versus other approaches such a self-aligned double pattering (SADP). The big advantage to LE2 is that the pattern produced can be 2D with metal runs in both the X and Y directions; the disadvantage is that the achievable minimum pitch isn’t as small as it is with SADP. For a foundry process flexibility in metal routing is very important and trading off some pitch for routing flexibility makes sense.
The Samsung 14LPE process also employs self-aligned vias. Basically the LE2 metal pattern is done first and memorized into a hard mask and then the via pattern is overlaid. The via pitches are also relaxed and this allows the vias to be single patterned.
Intel P1272 process
Intel develops microprocessor processes first and then adapts the processes for foundry later (typically around a year later). Because Intel controls both the process and the design for their microprocessors it allows them to impose much stricter design rules than a foundry can typically require and the P1272 process is an excellent example of this. For the first four metal layers Intel has used SADP with block masks. SADP creates a mandrel and then spacers on the mandrel edges doubling the mask pitch. SADP can in theory double an 80nm single exposure mask to a 40nm pitch. The drawback is the 40nm pitch is only achieved in one direction basically creating parallel lines and spaces in that direction. You get tightly spaced lines in the X direction but no lines in the Y direction. The lines also have to be cut or in the case of interconnect blocked by one or more additional masks.
By using SADP Intel has achieved pitches of 56nm, 70nm, 52nm and 56nm for the first four metal layers. These are however 1D gridded lines and spaces allowing much less metal routing flexibility. In fact to some extent what was a single 2D metal layer has to be broken up into two 1D metal layers. This has resulted in a significant increase in the number of metal layers required for the 14nm process. Intel’s 130nm, 90nm, 65nm, 45nm, 32nm and 22nm processes had 6, 7, 8, 9, 9, and 9 metal layers respectively, at 14nm the metals layers jumped to 13!
The Intel P1272 process also utilizes self-aligned via so the critical via are single patterned.
After reading this you may wonder which BEOL is better and the answer is it depends. For Intel’s microprocessor designs where they can impose very strict design rules Intel has undoubtedly done an exhaustive analysis to decide on their process. For Intel, foundry is a distant second to microprocessors in priority and I would suspect the process decisions were heavily weighted towards optimizing it for microprocessors. For Samsung the 14LPE process is a foundry process and needs to support more flexible metal routing. Intel achieves a tighter pitch on individual metal layers but depending on the routing requirements this may or may not achieve a denser design or may require additional metal levels and therefore higher process costs.
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