Intel Internal Foundry Model Webinar

Intel held a webinar today to discuss their IDM2.0 internal foundry model. On the call were Dave Zinsner Executive Vice President and Chief Financial Officer and Jason Grebe Corporate Vice President and General Manager of the Corporate Planning Group.

On a humorous note, the person moderating the attendee questions sounded a lot like George Takei who played Lieutenant Sulu on the original Star Trek. Since Intel is trying to accelerate what they are doing, warp 10 mister Sulu seems appropriate.

Under Intel’s historical business model, manufacturing and technology development costs were allocated to the business units and to Intel Foundry Services (IFS). The business units and IFS sold their product and had reportable profit and loss statements (P&L). Under the new model, manufacturing, technology development, and IFS will be a reportable P&L and will sell wafers to the Intel business units at market prices, see figure 1.

This realignment will put a big focus on the new Internal Foundry Business Unit (or whatever they decide to call it). The business units will have increasing freedom to choose processes from internal and external sources and the internal unit will have to compete on price and performance. It will also make it easier to benchmark the internal manufacturing against external foundries because they will be competing on price and with a standalone P&L the relative financial performance will be clear.

The new structure will force the business units to pay a premium for hot lots the same way fabless companies do at foundries. Apparently, Intel runs a lot of hot lots, and it is impacting capacity by 8 to 10%. As a former fab manager, I can confirm that hot lots are very disruptive to fab operations, I hated them and strictly limited how many could be in the fab at one time.

Intel expects that initially operating margins will be negative and as they scale up and address their cost structure, they expect to move positive, see figure 2.

Intel is delivering $3 billion dollars in cost reduction this year with $2 billion dollars in operating expense and $1 billion dollars in cost of sales savings, They are targeting $8 to $10 billion dollars in saving exiting 2025. Figure 3. Summarizes some identified savings opportunities.

In Q1 of next year the internal foundry business unit will have approximately $20 billion dollars of revenue making it the second largest foundry in the world. Virtually all the revenue in Q1 will be internal products but this is the same path Samsung has taken and they also have a lot of internal revenue.

I think this is an excellent realignment on Intel’s part to ensure their internal manufacturing is competitive on both a technology and cost basis.

One area in the presentation I have an issue with is the following slide, see figure 4.

The idea behind figure 4 is that Intel will be designing and piloting four products on each new node before external customers get access to the node so Intel will have worked through the early issues and customers will get a more mature process. In my opinion this shows a lack of understanding of the foundry model on Intel’s part. Leading edge fabless companies are not going to accept being many months or even a year behind the leading edge. At TSMC leading fabless customers are involved in the definition and testing of new processes and are lead customers so they can be first to market. A company like Apple is involved and pays to be first to market, they are not going to wait for Intel to launch the processes on their own products first.

There was a discussion on process technology. The five nodes in four-year message was repeated and it was noted two of the five nodes are now done and the other three are on track. I personally don’t count i7 as it is really a plus version of 10nm, but even four nodes in four years is impressive.

Historically Intel was a leader in process technology introducing a new process every two years. The way I have always thought about Intel processes is they will have a node n in high volume production, are ramping up a new node n+1, and ramping down a previous node n-1. They typically have 3 to at most 4 nodes running at any time and this means older nodes are being regularly retired.

Slide 7. Illustrates how Intel views the changes in the market.

When I look at this slide, I agree with the left side graph, capital intensity is increasing. I don’t completely agree with the middle graph. Yes, disaggregation will likely increase node tails, but the reality is the node tails have historically been far shorter for Intel than for the foundries because Intel is focused on leading edge microprocessors. TSMC is still running their first 300mm fab on 130nm that entered production in the early 2000s, Intel’s 130nm production shut down by the late 2000s. Disaggregation will help Intel use more trailing edge technology, but external foundry customers will likely be an even larger driver of trailing edge if Intel succeeds in the foundry business.

David Zinsner specifically mentioned that running fabs past their depreciable lifetime generates cash and increases margins. This is a key part of the success of the foundry model. TSMC is still running 130nm, 90nm, 65nm, 40nm, 28nm, and 16nm fabs that are fully depreciated and are the cash cows paying for new technologies and have the highest margins. It may seem counter intuitive but the newest nodes with high depreciation pull down TSMC’s corporate margin by a couple of points of the first two years. When a fab becomes fully depreciated the wafer cost drops more than half and the foundries only pass on some of that savings to the customers increasing gross margins.

The longer node life will be particularly critical for Intel going forward, with i4 ramping, i3 coming this year, and 20A, and 18A next year, all EUV based processes, under the old 3 nodes running policy Intel’s non EUV processes would all be disappearing by 2025. As I have written about previously, Intel has a large portfolio of fabs that will never convert to EUV and they will need a use for those fabs, external customers can provide that. That article is available here.

On the right side of figure 7. Intel lines up their processes and timing versus competitors. I agree that at 32nm and 22nm Intel was well ahead and at 14nm the lead narrowed and at 10nm they fell behind. I am not sure exactly what the criteria is for the alignment of i4, i3, 20A and 18A versus the competitor processes. Certainly, from a timing perspective it is correct, but how did they decide what Intel processes match up to what foundry processes? On a density basis I would say even 20A and 18A likely won’t match TSMC 3nm but on a performance basis they will likely exceed even TSMC 2nm.

During the call Dave Zinsner said Intel expects to announce their first 18A customer this year. During questioning he was asked what is holding up the announcement and he said it is maturity of the PDK. This matches up with what Daniel Nenni has been hearing that the Intel 18A models aren’t ready yet.

In conclusion, I believe that creating a P&L around Intel Internal Foundry is a positive step to help drive competitiveness. I don’t completely agree with all aspects of the message on this call but I do think that overall Intel is making good progress and moving in the right direction.

Some people have speculated this is a step toward Intel eventually splitting the company, I am not sure I see that happening, but this would likely make that easier if it ever happened.

Intel’s execution on process technology has gotten a lot better and is in my opinion the single biggest driver of their future success. The Tower acquisition wasn’t discussed but will in my opinion also be a key piece in finding external foundry business to fill all the Intel non EUV fabs.

Also Read:

The Updated Legacy of Intel CEOs

VLSI Symposium – Intel PowerVia Technology

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

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