IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier MiiThe main program for the 70th IEDM opened…Read More
How I learned Formal VerificationBing Xue is a dedicated Formal Verification Engineer at Axiomise,…Read More
Accellera 2024 End of Year UpdateFrom my viewpoint, standards organizations in semiconductor design…Read More
With the adoption of the 32/28 nm process node, some significant new challenges in digital routing arise—including complex design rule checking (DRC) and design for manufacturing (DFM) rules, increasing rule counts, very large (1 billion transistor) designs. To meet quality, time-to-market, and cost targets, design teams… Read More
After the mega IP acquisitions last year by Cadence (Denali) and Synopsys (Virage) a lot of people are wondering what is next for the commercial Semiconductor IP market. Let me offer my opinion as a person who works closely with foundries and their top customers and the opinion of Dr. Eric Esteve, an expert on interface IP.
The commercial… Read More
Intro
On Monday evening I talked with Linda Fosler, Director of marketing for the DSM Division at Mentor about what’s new at DAC this year in circuit simulation and IC layout tools.
Notes
IC Station – old name for IC layout tools
Eldo – Eldo Classic- Cell characterization
– ST is the early customer and teaching customer,… Read More
Intro
Across the aisle from the Mentor booth at DAC sat a DRC tool competitor to Calibre. I received an update from Randy Smith of Polyteda on Wednesday afternoon, my last EDA vendor of the week.
Ravi Ravikumar, Randy Smith
Notes
Randy Smith – CEO (February 2011) [former founder is gone]- 1979 at HP developing internal tools
–… Read More
Intro
Massimo Sivilotti, Ph.D of Tanner EDA showed me their 3D field solver in the HiPer PX extraction tool at DAC last week.
Notes
Tool Suites – schematics, layout, SPICE simulation, DRC/LVS
– HiPer PX: 3D Field solvero Layers, dielectrics,
o Finite element analysis
o Boundary element methods
o 2D mode for pattern matching… Read More
Intro
Show me what has changed in my RTL or Schematic since the last time I looked. This task is now automated by Cliosoft with their new hierarchical tool called Visual Design Difference (VDD). Srinath showed me what was new for DAC.
Srinath Anantharaman
Notes
LSI, STMicro – use DesignSync for their DM but use VDD for seeing visual… Read More
Intro
In the bloggers suite I met with John Pierce of Cadence last Wednesday to get an update on what’s new with circuit simulation at DAC this year.
Notes
News – market is growing, RF CMOS simulation is growing
– Show on RF (MTT – Microwave Technology ) this week, sharing a booth with AWR this week
– Recent news with… Read More
Intro
Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.
Notes
Why do this?
– Reduce leakage
– Increase gate lengths on paths with slack
–… Read More
Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.
Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired… Read More
Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.
Daniel Borgraeve (on right)
Notes
Edxact
– Started seven years ago… Read More
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