IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solidoare so passionate about this topic that they combined their years of experience into a book that I had a chance to read and review. Analog, AMS and even high-speed digital designers would benefit from the design ideas suggested in this book. I will give away one free copy of this book (retail value $120.00) to the person who comments on the blog with the best request.
The book has seven chapter that propose a variation-aware flow as shown below that is both fast and accurate:
Chapter 1: Introduction
IC designers have been using combinations of Process, Voltage Temperature (PVT) corners for years to determine how their design will work under varying conditions.
The Fast Fast (FF) and Slow Slow (SS) process corners do not really capture the bounds of the distribution for the average duty cycle output of a phase locked loop (PLL) voltage-controlled oscillator (VCO) on a GLOBALFOUNDRIES 28nm process.
Chapter 2: PVT Analysis
Choosing how many PVT corners to analyze, there are several approaches:
- Full factorial
- Guess worst-case
- Guess worst-case plus full verification
- Fast PVT
The third step in the variation-aware flow is an automated one where worst-case corners are automatically extracted for your specific design and process called Fast PVT, in contrast to older methodologies where a designer would guess at which PVT corners to use as worst-case or simply create hundreds to thousands of corners for analysis.
Chapter 3: Primer on Probabilities
Probability Density Functions (PDF) are introduced in a visual approach using scatterplots, histograms and Normal Quantile (NQ) plots. This is a precursor to chapters 4 and 5, the statistical chapters.
Chapter 4: Three-sigma Statistical Analysis
To design with target yields of two to three sigma (95 to 98.6%) there are several design flow approaches:
- PVT with SPICE
- PVT with +- 3 stddev Monte Carlo Verify
- PVT plus binomial Monte Carlo Verify
- PVT with Convex Models
- Direct Monte Carlo
- Light plus Heavy Direct Monte Carlo
- Linear Worst-Case Distances
- Quadratic Worst-Case Distance
- Response Surface Modeling
- Sigma-Driven Corners (preferred)
Comparison of three-sigma approaches
Chapter 5: High-sigma Statistical Analysis
To achieve high sigma analysis several possible approaches are considered:
- Giant Monte Carlo
- Medium Monte Carlo
- Monte Carlo with Extrapolation
- Manual Model
- Quasi Monte Carlo
- Direct Model-based
- Linear Worst-Case Distance
- Rejection Model-Based
- Control Variate Model-Based
- Markov Chain Monte Carlo
- Importance Sampling
- Worst-Case Distance plus Importance Sampling
- High-Sigma Monte Carlo (preferred)
Three actual design examples (flip-flop, DRAM, SRAM sense amplifier) are provided showing High-Sigma Monte Carlo (HSMC) results.
Distribution of flip-flop setup time. Data is from a Monte Carlo run with 1,000 samples.
Chapter 6: Variation-aware Design
To actually change transistor sizes in your design so that it yields optimally across variation there are several design methods:
- Manual design (hand-based analysis and design, SPICE-based analysis and design)
- Automated design (automated topology design, automated sizing)
- Integrated Manual and Automated (preferred)
A tool to help integrate manual and automated design should be able to guide the user towards making the greatest benefit design choices first. Here’s a conceptual example of an interactive design exploration interface:
The $120 that you spend on this book will certainly save your company many times that amount by changing your IC design flow to be variation-aware with a Fast PVT approach. Older, brute-force Monte Carlo approaches take too much simulation time, and may not be catching the worst-case conditions needed to ensure that your IC design is tolerant to variations.
I appreciated that the authors made this a field guide showing many approaches and sharing their actual design experience, rather than an EDA tool product pitch.Share this post via: