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TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes

TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
by Daniel Nenni on 05-10-2016 at 12:00 pm

 Being that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from Solido:

  • Major Customers Served: 35
  • User Driven Enhancements: 612
  • 1-on-1 Sessions Completed: 2120

If you look at theSolido landing pageyou will see 36 different blogs written by 6 different people from a variety of perspectives. These blogs have been viewed more than 165,000 times resulting in some very interesting discussions in the comment sections. The blogs started at 40nm but really picked up at 28nm and 20nm. At 16nm, 14nm, and now 10nm process variation is a well documented FinFET fact of life so there is no more speculation about if and when variation will be a serious threat.

Tom Dillinger (Chipguy) wrote the most recent Solido blogs highlighting their latest 4.0 software release. Tom is infamous for his love of coffee, knowledge of designing with FinFETs, and writing about it in great detail so you should definitely take a look at these blogs as a primer for the webinar:


  • A Better Way for Analog Designers to Perform Variation Analysis
  • Improvements in SRAM Yield Variation Analysis

    Which brings us to the upcoming webinar with TSMC who is both a long time Solido partner and customer:

    TSMC and Solido Collaborate for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes


    Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule. This webinar will discuss on how TSMC and Solido collaborate to offer variation-aware design techniques for memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.

    IC Designers • Design Managers • CAD Managers • Directors

    What the Audience Will Learn:
    Variation-aware design techniques for high-performance, low-power, low-cost products for memory and standard cell.


    Jacob Ou

    Technical Marketing Manager, TSMC
    Jacob Ou is a technical manager at TSMC. He has more than 8 years of experience in simulators, PDK, router and worldwide customer support. His role at TSMC is managing EDA-related projects with the engineering team addressing simulation and STA challenges at the most advanced nodes. He received his MSEE from National Cheng Kung University.

    Kristopher Breen
    VP Customer Applications, Solido
    Kristopher Breen is Vice President, Customer Applications at Solido Design Automation. He has over 11 years of experience managing the development, deployment, and support of variation-aware design and verification solutions for customers worldwide. Breen is also co-author of Variation-Aware Design of Custom Integrated Circuits: A Hands-On Field Guide. He received his M.Sc. in Electrical and Computer Engineering from the University of Alberta, Canada.

    What is Solido?
    Solido Design Automation is the leading provider of variation management software, including the best-in-class tool, Variation Designer. Used by over 1000 designers at more than 35 major companies worldwide, Variation Designer is the world’s most advanced variation-aware design technology. The production-proven and versatile toolset is the easiest to use in its class and unparalleled in customer responsiveness.

    The importance of variation-aware design is only increasing with greater power demands, decreasing margins, and smaller and more advanced technology nodes. Managing statistical variation to select better design tradeoffs and avoid product failures is a huge challenge in memory, analog/RF and standard cell custom IC design, but by doing so, designers produce more competitive products in shorter design cycles and with fewer respins. Solido has proven that Variation Designer is the best solution for solving real production problems, meeting the challenges of its customers in day-to-day design.

    Variation Designer is positioned to continue as the most advanced variation-aware design technology because of Solido’s rich culture of innovation, dedication to producing high-caliber software, and ability as an agile company to focus on the most difficult challenges faced by the industry. We work closely with our customers to push the limits of design and are challenged ourselves to more efficient and inventive solutions.

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