TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes

TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
by Daniel Nenni on 05-10-2016 at 12:00 pm

Image RemovedBeing that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from… Read More


A Better Way for Analog Designers to Perform Variation Analysis

A Better Way for Analog Designers to Perform Variation Analysis
by Tom Dillinger on 04-18-2016 at 7:00 am

Image RemovedThe impact of process variation at advanced nodes is increasing — no surprise there. In recent years, the principal design emphasis to better reflect this variation has been the adoption of two new methodologies: (1) advanced on-chip variation (AOCV, as well as POCV/LVF) for digital static timing analysis,… Read More


Improvements in SRAM Yield Variation Analysis

Improvements in SRAM Yield Variation Analysis
by Tom Dillinger on 03-27-2016 at 12:00 pm

Image RemovedThe design of an SRAM array requires focus on the key characteristics of readability, writeability, and read stability. As technology scaling has enabled the integration of large (cache) arrays on die, the sheer number of bitcells has necessitated a verification methodology that focuses on “statistical high-sigma… Read More