The RISC-V and Open-Source Functional Verification ChallengeMost of the RISC-V action at the end…Read More
Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers2.5D package design is rapidly finding its stride…Read More
Addressing Reliability and Safety of Power Modules for Electric VehiclesAs electric vehicles (EVs) gain widespread adoption, safety,…Read More
Shaping Tomorrow’s Semiconductor Technology IEDM 2024Anyone who has read my articles about IEDM…Read More
SI and PI Update from Cadence on Sigrity XSignal Integrity (SI) and Power Integrity (PI) issues…Read More
As I mentioned in my previous blog, AMD and GlobalFoundries,it is rather difficult to interpret AMD’s financial results. At the end of the quarterly earnings conference calls analysts get to ask questions. It is the comedy relief portion of the call usually, so I blog this today to better prepare these so called analysts … Read More
As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.
Please take this anonymous 16 question survey to identify critical Design for Manufacturability (DFM) issues facing… Read More
I have been saying for years, ever since I started working at VaST, the biggest barrier to adoption of virtual platform technology for what I like to call virtualized software development is the availability of models. If models do not already exist when they are needed there are two issues: it takes money to develop them but, probably… Read More
This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More
At DAC in 2011 I visited an EDA company called Silicon Frontline Technology because they offered some 3D field solver tools used to create the highest accuracy netlists that can then be simulated with a SPICE circuit simulator to predict timing, power and IR drop. A recent press release with X-FAB and Silicon Frontline looked interesting… Read More
The EDAC Emerging Companies Comittee (would that be the EDACECC?) is organizing a free panel session one evening at DVCon. It is Monday February 27th from 6pm to 8.30pm. I don’t yet have a room but it will be at the DoubleTree Hotel where DVCon is being held.
EDA companies often address hardware/software co-design from a hardware… Read More
A client turned me on to a great new book, “The Age of the Platform” by Phil Simon. It’s about how Amazon, Apple, Facebook, and Google have radically transformed the landscape. For me, it’s not just social networking – it’s social computing, changing how things are designed.
I’m borrowing this right from Phil’s… Read More
It is interesting watching as changes in technology bring giants to their knees. Far and away the best book on the subject is Clayton Christensen’s The Innovator’s Dilemma. If you haven’t read it then rush out and buy it immediately. In tech, you are not educated if you haven’t.
Two things made me think … Read More
FineSim is Magma’s circuit simulator that has been doing extraordinarily well. In my opinion it is one of the big reasons that Synopsys is acquiring (presumably, still subject to approval of course) Magma. FineSim is especially strong in the memory market with over 70% of the top 5 DRAM manufacturers and the top 10 flash manufacturers… Read More
Things you don’t know about Virtuoso: we’ve got you cornered.
That is the title on a Cadence blog item last week. It is actually about variability and how to create various corners for simulation and analysis, but given Cadence’s franchise for Virtuoso, its lock-in through SKILL-based PDKs and so forth, it … Read More
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