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No, gosh darn it, I said the NFC is near!

No, gosh darn it, I said the NFC is near!
by Don Dingee on 03-22-2012 at 11:24 am

Getting a feature to take off in today’s smartphone market is tricky. It requires a combination of hardware support, OS support, app integration, and maybe most importantly carrier adoption. Ideas that seem ready technologically, like NFC, get stopped in their tracks by silly things like the William J. LePetomaine Thruway… Read More


What’s Up with SNUG This Year in Santa Clara?

What’s Up with SNUG This Year in Santa Clara?
by Daniel Payne on 03-22-2012 at 11:04 am

Next week is a big deal because it’s when Synopsys has their annual user group meeting, SNUG in Santa Clara at the Convention Center from Monday through Wednesday. I’d love to hear if they have made any decisions on the new product roadmap after the Magma acquisition, although it’s probably too early to tell.… Read More


3D-IC Testing – A 3D perspective to SoC

3D-IC Testing – A 3D perspective to SoC
by Pawan Fangaria on 03-21-2012 at 9:30 am

In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory… Read More


According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012

According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
by Eric Esteve on 03-21-2012 at 9:10 am

The launch from Cadence of the PCI Express 3.0 Controller IP was officially done about one year ago, and demonstrated at the June 2011 PCI-SIG Developer’s Conference, where Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller… Read More


Apple’s Leveling of the Semiconductor Industry

Apple’s Leveling of the Semiconductor Industry
by Ed McKernan on 03-20-2012 at 2:03 pm

Holman Jenkins, the distinguished writer of business trends for the Wall St. Journal, recently penned an article entitled “The End of Apple’s Roach Motel?” (Personally, I think that since Apple is in California, he should have used Hotel California in his title), questioning the iPhone and iPAD maker of its ability to continue… Read More


A Chat with John Stabenow

A Chat with John Stabenow
by Daniel Payne on 03-20-2012 at 10:57 am

John Stabenow is the marketing group director at Cadence for the Virtuoso products and it has been awhile since we last talked, so we met for lunch on Friday at McMenamins in a city called West Linn, half-way between where we both live in Oregon. I had blogged about Interoperability at DAC 2010 and we had a public exchange at Chip Design… Read More


GLOBALFOUNDRIES Dresden Fab 1

GLOBALFOUNDRIES Dresden Fab 1
by Daniel Nenni on 03-18-2012 at 6:00 pm

Even though my Dresden trip was fraught with fail points it went off without a hitch. Flying over was easy, I connected through London Heathrow, flying back I connected through Frankfurt. The last time I connected through Frankfurt was right after the 9/11 attacks so I had a bit of deja vu. I was in Munich, Heathrow was closed, I was … Read More


EDPS Monterey

EDPS Monterey
by Paul McLellan on 03-17-2012 at 8:00 am

Every year in Monterey is a relatively small conference that looks at the design process, EDPS, the electronic design process symposium. I gave a keynote there a couple of years ago, but you don’t have to listen to me this time. The keynotes are from:

  • 1st day: Misha Buric, CTO of Altera, talking about SoC FPGAs and other things
Read More

Double Patterning and Then The End of Lithography

Double Patterning and Then The End of Lithography
by Paul McLellan on 03-15-2012 at 8:00 am

I went to a couple more sessions at the Common Platform Technology Forum today, on 20nm double patterning and whatever will we do at 14nm. Basically, this is the end of planar transistors and the end of optical lithography. One session was by IBM scientists about process and one by Michael White of Mentor about double patterning. … Read More


No Semiconductor Design Cloud Strategy? Really?

No Semiconductor Design Cloud Strategy? Really?
by Andrea Casotto on 03-14-2012 at 6:00 pm


I ask my customers about their cloud strategy and they all tell me “none”. The main reason is a red herring: “The legal department will never allow our IP outside our walls”.

Security issues on the cloud are largely solved, as proven by the fact that banks have no problem using external clouds. Behind the curtain, the real reason for… Read More