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Introduction to FinFET technology Part I

Introduction to FinFET technology Part I
by Tom Dillinger on 04-18-2012 at 6:00 pm

This is the first of a multi-part series, to introduce FinFET technology to SemiWiki readers. These articles will highlight the technology’s key characteristics, and describe some of the advantages, disadvantages, and challenges associated with this transition. Topics in this series will include FinFET fabrication,Read More


Linley Tech Mobile Conference

Linley Tech Mobile Conference
by Paul McLellan on 04-18-2012 at 2:14 pm

I went to part of the Linley Tech Mobile Conference. This is the current incarnation of what started life as Michael Slater’s Microprocessor Report, and the twice-yearly Microprocessor Forum. These very technical analysis organizations seem to work well when they are a small group of analysts working together to cover… Read More


Analog Circuit Optimization

Analog Circuit Optimization
by Daniel Payne on 04-18-2012 at 2:06 pm

Gim Tan at Magma did a webinar on analog circuit optimization, so I watched it today to see what I could learn about their approach. Gim is a Staff AE, so not much marketing fluff to wade through in this webinar.

The old way of designing custom analog circuits involves many tedious and error prone iterations between front-end (Schematic… Read More


Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)

Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)
by Daniel Payne on 04-18-2012 at 12:38 pm

Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you’re in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a … Read More


ARM Seahawk

ARM Seahawk
by Paul McLellan on 04-17-2012 at 8:27 pm

I wrote on Monday about ARM’s Processor Optimization Packs (POPs). In Japan they announced yesterday the Seahawk hard macro implementation in the TSMC 28HPM process. It is the highest performance ARM to date, running at over 2GHz. It is a quad-core Cortex A15.

The hard macro was developed using ARM Artisan 12-track libraries… Read More


Previewing Intel’s Q1 2012 Earnings

Previewing Intel’s Q1 2012 Earnings
by Ed McKernan on 04-17-2012 at 9:15 am

Since November of 2011 when Intel preannounced it would come up short in Q4 due to the flooding in Thailand that took out a significant portion of the HDD supply chain, the analysts on Wall St. have been in the dark as to how to model 2012. Intel not only shorted Q4 but they effectively punted on Q1 as well by starting the early promotion… Read More


Laker Wobegon, where all the layout is above average

Laker Wobegon, where all the layout is above average
by Paul McLellan on 04-17-2012 at 4:00 am

TSMC’s technnology symposium seems to be the new time to make product announcements, with ARM and Atrenta yesterday and Springsoft today.

There is a new incarnation of Springsoft’s Laker layout family, Laker[SUP]3[/SUP] (pronounced three, not cubed). The original version ran on its own proprietary database.… Read More


Soft Error Rate (SER) Prediction Software for IC Design

Soft Error Rate (SER) Prediction Software for IC Design
by Daniel Payne on 04-16-2012 at 10:00 am

My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate… Read More