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After Planning Comes Implementation for Pulsic

After Planning Comes Implementation for Pulsic
by Paul McLellan on 05-24-2012 at 7:00 am

Automation for digital design has been mainstream for a couple of decades but place and route for analog is still in its infancy. Many attempts have been made over the years to automate analog design in one way and another, the bodies are piled up on the hillside. Much analog design is still largely done with custom layout and circuit… Read More


Software-based Wi-Fi: DSP IP core

Software-based Wi-Fi: DSP IP core
by Eric Esteve on 05-23-2012 at 10:05 am

The recent announcement from CEVA that it has joined the Wi-Fi Alliance® to further advocate for a software-based Wi-Fi® strategy shows that the new CEVA-XC4000 DSP can be used in various communication protocols, not limited to the traditional baseband processing for the wireless handset phone, where DSP IP core usage is massive.… Read More


Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap

Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap
by Daniel Nenni on 05-22-2012 at 9:00 pm

The introduction of 28nm high-volume production for IC semiconductor devices will usher the era of “extreme low-k1” manufacturing, i.e. the unprecedented situation in the long history of the silicon technology roadmap, where computationally intensive (and EDA-driven) Design-Technology Co-Optimization will become the… Read More


The Midwestern Hedge Fund Manager

The Midwestern Hedge Fund Manager
by Ed McKernan on 05-22-2012 at 7:06 pm

Four years ago, a VC friend of mine was invited to a get together with a prominent Hedge Fund Manager from the Midwest. The meeting was an arrangement between fellow Harvard Grads. The Fund Manager was looking to make investments in the valley, to diversify away from his heavily weighted financial positions. Though, not recognized… Read More


Intel Tri-Gate is in Trouble?!?!?!

Intel Tri-Gate is in Trouble?!?!?!
by Daniel Nenni on 05-22-2012 at 6:00 pm

Since the last Intel logo parody went over so well here is another one! Not so much a parody in light of the recent PR from Intel that the fabless semiconductor business model is doomed. As one of the doomed little people inside the fabless ecosystem I take exception to this but I digress….

The word around Silicon Valley is that Intel … Read More


DAC 2012…need caffeine?

DAC 2012…need caffeine?
by Paul McLellan on 05-21-2012 at 5:00 pm

You are in San Francisco for DAC and you want a coffee. OK, if your booth duty is 5 minutes away you pretty much have to take the Moscone coffee. Tastes good, hot, has caffeine. As Meatloaf used to sing (showing my age here) two out of three ain’t bad.

Yes, there are Starbucks all over the city, one on 4th Street just by Moscone Center,… Read More


AMS Programmable Prototype Platforms

AMS Programmable Prototype Platforms
by ahmed.shahein on 05-21-2012 at 10:25 am

AVNET released their 15[SUP]th[/SUP] Xfest this year, a couple of months ago. It was here in Germany last week. It was a well organized event, rich with invaluable technical information and full of decent smart engineers and managers. If you missed it this year register for the next event as soon as you can.

It was a very successful… Read More


EDAC Emerging Companies: Learn How to Emerge

EDAC Emerging Companies: Learn How to Emerge
by Paul McLellan on 05-20-2012 at 9:00 pm

EDAC has a series of seminars for emerging companies with Jim Hogan. Jim has been in EDA since, like, forever. First at National, then at Cadence, then at Artisan (now ARM) and then as an investor first at Telos (Cadence’s VC arm) and more recently on his own at Vista Ventures. He has been involved with many EDA and semiconductor… Read More


Layout Migration and DRC Correction at DAC 2012

Layout Migration and DRC Correction at DAC 2012
by Daniel Nenni on 05-20-2012 at 5:00 pm

In the world of sub-40nm IC design, as feature size decreases with each new process node, it becomes increasingly difficult to migrate a layout to a new process technology. Too many factors impact manufacturability and yield. At each new process node, to make sure that a given layout is manufacturable and yields well, it is subject… Read More


Going with the Flow at AMD

Going with the Flow at AMD
by Paul McLellan on 05-19-2012 at 11:00 am

At EDPS in Monterey, Tom Spyrou of AMD talked about their compute environment in the context of parallel algorithms. I discovered that they are a big user of RTDA’s FlowTracer so I talked to Philip Steinke at AMD about how they used it.

He said that they largely use it as described in The Art of Flows as a graphical distributed … Read More