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At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT
by Graham Bell on 02-24-2013 at 8:10 pm

By now, you will have seen several postings about all the different activities that are going on at Design and Verification Conference being held Feb. 25-28 at its usual location – the DoubleTree Hotel in San Jose, CA. Besides organizing an experts panel “Where Does Design End and Verification Begin?“, Real Intent with Calypto Design Systems and DeFacTo Technologies are presenting a joint tutorial on Thursday afternoon – “Pre-Simulation Verification for RTL Sign-Off“.

It is interesting to note that the Big Three EDA companies each have their tutorials on Thursday morning, and three companies from the next-tier each have a tutorial in the afternoon. Conference attendees will have the tough decision of picking which tutorial to attend. I wanted to share with the SemiWiki audience some quick insights on the pre-simulation verification topic and a slide that will be presented next week.

The scope of pre-simulation verification is so broad it is not covered by any one company. While it might be argued one of the big three can do it all, I think they would not claim to have a best-in-class solution for the different problem areas that specific attention at the RT-level.

What are the specific areas that need attention? In the tutorial we will be covering power exploration, analysis and optimization using an abstract model with high-level synthesis (HLS), followed by the RTL static verification for: syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; clock domain crossing sign-off; Design-For-Test analysis and insertion; and X-analysis and related optimism and pessimism correction.

This slide from the presentation gives a quick illustration of the entire flow. The benefits are early elimination of complex bugs before simulation, and early closure on power and DFT before the gate-level.

There is a lot of material to cover and I think this joint tutorial with Calypto and DeFacTo will make it clear what needs to happen before simulation (and synthesis) so teams have a design have RTL that is signed-off for implementation.


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