At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT
by Graham Bell on 02-24-2013 at 8:10 pm

By now, you will have seen several postings about all the different activities that are going on at Design and Verification Conference being held Feb. 25-28 at its usual location – the DoubleTree Hotel in San Jose, CA. Besides organizing an experts panel “Where Does Design End and Verification Begin?“, Real… Read More