At DAC 2012 we were hearing about the 20nm design ecosystem viability, however IC process technology never stands still so we have early process development going on now at the 10nm and 14nm nodes where FinFET technology is being touted. Earlier in February Vassilios Gerousis, a distinguished engineer at Cadence presented a session at the Common Platform Technology Forum: Next Generation R&D and Advanced Tools for 14nm and Beyond. Richard Goering blogged about this.
There have already been three tapeouts at 14nm using FinFET test chips:
- Cadence, ARM – Cortex M0, IBM – SOI
- Cadence, ARM – SRAM macros, Samsung – Bulk CMOS
- Cadence, ARM – Cortex-A7, Samsung – Bulk CMOS
The mantra of collaboration continues into 2013, as EDA vendors, foundries and design, all combine into a virtual team to get the IC design job done. Double patterning (DPT) started at the 20nm node and continues at 14nm and 10nm, however with an additional wrinkle called litho-etch, litho-etch or LELE to create yet another acronym. With LELE the foundry is exposing and etching more than once using alternating masks.
At the 10nm node there’s a new block mask added which is part of the Self-Aligned Double Patterning (SADP) where relief patterns are created, sidewalls are deposited, and finally the unintended shapes are trimmed away. That’s way more complex than DPT at 20nm.
EDA tools like routers need to take into account at 10nm things like:
- Color-mappable rule set
- Block masks
- Sidewall Image Transfer (SIT) effects
With FinFET transistors the width of the devices are quantized, instead of having continuous width ranges.
Cadence has a FinFET tool flow and for circuit simulation there’s a BSIM-CMG device model which they helped develop:
All of this research will help ensure that SoC designers will have proven IP and EDA tool methodology in place, within a few years to exploit 14nm and 10nm nodes. I look forward to hearing about the silicon results of these test chips.