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Early Test –> Less Expensive, Better Health, Faster Closure

Early Test –> Less Expensive, Better Health, Faster Closure
by Pawan Fangaria on 09-18-2013 at 11:00 am


I am talking about the health of electronic and semiconductor design, which if made sound at RTL stage, can set it right for the rest of the design cycle for faster closure and also at lesser cost. Last week was the week of ITC(International Test Conference) for the Semiconductor and EDA community. I was looking forward to what ITCRead More


Mentor Teaches Us About the Higg’s Boson

Mentor Teaches Us About the Higg’s Boson
by Paul McLellan on 09-17-2013 at 4:46 pm

Once a year Mentor has a customer appreciation event in Silicon Valley with a guest speaker on some aspect of science. This is silicon valley, after all, so we all have to be geeks. This year it was Dr Sean Carroll from CalTech on The Particle at the End of the Universe, the Hunt for The Higg’s Boson and What’s Next.

Wally … Read More


EDAC Export Seminar: Don’t Know This Stuff…Go Directly to Jail…Do Not Pass Go

EDAC Export Seminar: Don’t Know This Stuff…Go Directly to Jail…Do Not Pass Go
by Paul McLellan on 09-17-2013 at 2:04 pm

I am not making this up: All exports from the United States of EDA software and services are controlled under the Export Administration Regulations, administered by the U.S. Department of Commerce’s Bureau of Industry and Security (BIS). You need to understand these regulations. Failure to comply can result in severe … Read More


Are 28nm Transistors the Cheapest…Forever?

Are 28nm Transistors the Cheapest…Forever?
by Paul McLellan on 09-17-2013 at 10:43 am

It is beginning to look as if 28nm transistors, which are the cheapest per million gates compared to any earlier process such as 45nm, may also be the cheapest per million gates compared to any later process such as 20nm.

What we know so far: FinFET seems to be difficult technology because of the 3D structure and so the novel manufacturing… Read More


TSMC’s 16FinFET and 3D IC Reference Flows

TSMC’s 16FinFET and 3D IC Reference Flows
by Paul McLellan on 09-17-2013 at 2:01 am

Today TSMC announced three reference flows that they have been working on along with various EDA vendors (and ARM and perhaps other IP suppliers). The three new flows are:

  • 16FinFET Digital Reference Flow. Obviously this has full support for non-planar FinFET transistors including extraction, quantized pitch placement, low-vdd
Read More

How to Design an LTE Modem

How to Design an LTE Modem
by Paul McLellan on 09-16-2013 at 4:24 pm

Designing an LTE modem is an interesting case study in architectural and system level design because it is pretty much on the limit of what is possible in a current process node such as 28nm. I talked to Johannes Stahl of Synopsys about how you would accomplish this with the Synopsys suite of system level tools. He is the first to admit… Read More


Intel Bay Trail Fail

Intel Bay Trail Fail
by Daniel Nenni on 09-15-2013 at 5:00 pm

Now that the IDF 2013 euphoria is fading I would like to play devil’s advocate and make a case for why Intel is still not ready to compete in the mobile market. It was very clear from the keynotes that Intel is a chip company, always has been, always will be, and that will not get them the market share they need to be relevant in mobile electronics,… Read More


Semiconductor Manufacturing in India?

Semiconductor Manufacturing in India?
by Pawan Fangaria on 09-15-2013 at 11:30 am


Last week I heard about the Indian Cabinet approving the proposal for setting up of two Fabs in India. One led by IBM, Tower Jazzand JP Associates(an Indian business house), and the other led by HSMC(Hindustan Semiconductor Manufacturing Co.), ST Microelectronicsand Silterra. Indian Semiconductor community including IESARead More


Sidense and TSMC Processes

Sidense and TSMC Processes
by Paul McLellan on 09-14-2013 at 2:21 pm

I’ve written before about the basic capabilities of Sidense’s single transistor one-time programmable memory products (1T-OTP). Just to summarize, it is an anti-fuse device that works by permanently rupturing the gate oxide under the bit-cells storage transistor, something that is obviously irreversible.… Read More


Back To The Future: 50th Anniversary of EDA

Back To The Future: 50th Anniversary of EDA
by Paul McLellan on 09-12-2013 at 1:03 pm

October 16[SUP]th[/SUP] at the Computer History Museum, EDAC is hosting EDA: Back to the Future to celebrate 50 years of EDA. EDAC always has a fall event of some sort and historically it has been the Kaufman Award Dinner. This year, the Kaufman Award was presented (to Chenming Hu) at 50[SUP]th[/SUP] DAC, so the fall EDAC calendar… Read More