Sure, design engineers can get more attention than verification engineers, but the greater number of verification engineers on SoC projects means that the verification task is a bigger bottleneck in a schedule than pure design work. A recent survey conducted at Cadence shows how verification effort can be divided into several, distinct tasks:
The largest portion of verification time is spent in debugging, followed by the actual test execution run time. Speeding up the time spent on debug would directly benefit any SoC schedule. You can debug by printing out internal node values and staring at waveforms, while rerunning verification tests to try and pinpoint each error. If you didn’t add the right internal node, then you have to find it, add it and rerun verification tests, creating an iterative and slow debug process. There has to be a more elegant approach to debug.
Engineers at Cadence have come up with a better and patented methodology to quickly find bugs using Root Cause Analysis (RCA) technology. With the RCA approach you start by running a verification test, an output mismatch is detected by your testbench, then the underlying bug is found by using Big Data concepts. You then fix your identified bug, and re-run verification, thus reducing the number of brute force iterations previously used.
Big Data analysis looks at the entire design space in a single verification run while performing three functions to identify the actual root cause of the mismatches:
- SmartLog – capture all messages (SystemC, Verilog, etc.)
- Reverse debugging – ability to go forward and backward in time
- Multi-engine data – from functional simulation, formal tools, etc.
This totally new debugging platform is named Indago, and it has three apps that may be used either stand-alone or concurrently based on what you are looking for:
- Indago Debug Analyzer App – multi language testbench debug (SystemVerilog, e, SystemC), reverse debug, UVM debug, macro debug
- Indago Embedded SW Debug App – for embedded SW/HW integration debugging
- Indago Protocol Debug App – works with Cadence Verification IP (ARM AMBA AXI and ACE, DDR4)
Using the GUI in the debug analyzer you can pinpoint what caused the mismatched output value to change, this helps guide you and automates the bug tracking process. SmartLog lets you preview and filter results quickly.
SW engineers can debug to the source-code level and see how their code impacts output waveforms in the hardware.
With the channel viewer you can see VIP (Verification IP) results, step through each FSM (Finite State Machine) state and transitions, and use the source code debugger. Expect Cadence to grow the number of supported protocols over time.
Users of Indago would include SW engineers, HW design engineers and verification engineers.
There are basically three generations of debugging available: Basic, Mainstream and Advanced. Indago gets you to the advanced debugging capabilities.
The learning curve for Indago is typically just an hour or two to start getting your first results. Early customers are saying that they have cut their debug times in half, so imagine what that means on your SoC project. When I spoke with Kishore Karnaneand Adam Sherer of Cadence last week, they said that early adopters are using Indago now, while general availability is expected in June around time for the 52nd annual DAC show. The internal VIP group at Cadence is also a big user of Indago to help speed their products to market quicker and with higher quality.