All Things Semiconductor!
WEBINAR: Generating and Measuring IP Security Threat Levels For Your SoCsIPs have an attack surface that indicates how…Read More
Webinar - AI/ML SoC Memory and Interconnect IP PerspectivesFor decades development work on Artificial Intelligence (AI)…Read More
5G Deployments – The Analysis Requirements are GinormousThe introduction of 5G communications support offers tremendous…Read More
A Future Vision for 3D Heterogeneous PackagingAt the recent Open Innovation Platform® Ecosystem Forum…Read More
Image RemovedThe first of the low power webinars is coming up on July 19th at 11am Pacific time. The webinar will be conducted by Preeti Gupta, Sr. Technical Marketing Manager at Apache Design Solutions. Preeti has 10 years of experience in the exciting world of CMOS power. She has a Masters in Electrical Engineering from Indian … Read More
Image RemovedAnother announcement of interest, given all the discussion of Intel’s 22nm process around here, is that Samsung (along with ARM, Cadence and Synopsys) announced that they have taped out a 20nm ARM test-chip (using a Synopsys/Cadence flow).
An interesting wrinkle is that at 32nm and 28nm they used a gate-first… Read More
Image RemovedCadence this morning announced that it has acquired Azuro. Azuro has become a leader in building the clock trees for high performance SoCs. A good rule of thumb is that the clock consumes 30% of the power in an SoC so optimizing it is really important. Terms were not disclosed.
The clock trees involve clock gating which… Read More
Image RemovedAt DAC I talked with Mike Dimelow of ARM about the latest upcoming revision to the AMBA bus standards, AMBA 4. The standard gets an upgrade about every 5 years. The original ARM in 1992 ran at 10MIPS with a 20MHz clock. The first AMBA bus was a standard way to link the processor to memories (through the ARM system bus ASB) … Read More
Image RemovedDesign for test (DFT) imposes various restrictions on the design so that the test automation tools (automatic test pattern approaches such as scan, as well as built-in self-test approaches) will subsequently be able to generate the test program. For example, different test approaches impose constraints on clock… Read More
Intel’s new Tri-Gate technology is causing quite a stir on the stock chat groups. Some have even said if Intel uses its Tri-Gate technology on only Intel processors ARM will be in deep deep trouble. These guys are “Intel Longs” of course and they are battling “Intel Shorts” with cut and paste news clips.
Image Removed
“ARM is in trouble… Read More
At DAC 2011 in San Diego, Apache gave many product presentations. Of course not everyone could make DAC or could make all the presentations in which they were interested. So from mid-July until mid-August these presentations will be given as webinars. Details, and links for registration, are here on the Apache website.
Image Removed… Read More
During last week-end, I had the good surprise to meet with one of my oldest friend, Eric, who remind me the old time, when we were working together as ASIC designers for… a Supercomputer project.
In France, in a French company (Thomson CSF) active in the military segment and being able to spend which was at that time a fortune ($25M) … Read More
Interesting notes from my most recent Taiwan trip: Taiwan unemployment is at a record low. Scooters once again fill the streets of Hsinchu! TSMC will be passing out record bonuses to a record amount of people. TSMC Fab expansions are ahead of schedule. The new Fab 15 in Taichung went up amazingly fast with equipment moving in later… Read More
In my rush on Wednesday at DAC I had almost over-looked the last two companies I talked with: Invarian and AnaGlobe. These last two I had hand-written notes on paper, so I just got to the bottom of my inbox tonight to write up the final trip reports.
Invarian
Jens Andersen and Vladimir Schellbach gave me an overview of tools that perform… Read More
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better_recent_comments-2
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Widget_Better_Recent_Comments
Response to IP’s Growing Impact On Yield And Reliability