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                    [post_date] => 2012-03-13 20:16:00
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                    [post_content] => The SICAS (Semiconductor Industry Capacity Statistics) program has been discontinued after the release of the 4Q 2011 data, available through the SIA at http://www.sia-online.org/industry-statistics/semiconductor-capacity-utilization-sicas-reports/

The latest report stated: “Due to significant changes in the SICAS program participation base in 2011, the quarterly SICAS capacity and utilization report will be discontinued, effective Quarter 1 2012.” SICAS lost the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) and United Microelectronics Corporation (UMC) beginning in 2Q 2011. SICAS members likely questioned the value of continued participation without the two largest wafer foundry companies.

The end of SICAS is a major disappointment. The semiconductor industry has lost the definitive source of capacity and utilization data, a key component in determining the current and near term industry conditions. It is especially disappointing to me since I served on the founding executive committee of SICAS in 1995.

The death of SICAS follows the withdrawal of Intel and Advanced Micro Devices (AMD) from World Semiconductor Trade Statistics (WSTS) as originally reported in the Wall Street Journal: http://www.djnewsplus.com/rssarticle/SB133045771410082239.html
Without Intel and AMD, it will be extremely difficult for WSTS to report accurate statistics for microprocessors. Intel and AMD account for over 90% of the microprocessor market and microprocessors account for about 15% of the semiconductor market. WSTS may need to drop microprocessors from its product coverage, which would result in WSTS no longer being a reliable source of data on the overall semiconductor market.

As with the loss of SICAS, the loss of Intel and AMD in WSTS is a significant disappointment. I was Texas Instrument’s representative to WSTS for 14 years and served a term as WSTS chairperson. However I believe WSTS will adapt and survive. The organization provides detail on numerous product and application markets which provide vital information to member companies and industry analysts.

Final SICAS data


The chart below shows SICAS data for total IC capacity in thousands of eight-inch equivalent wafers per week. Capacity for TSMC and UMC was added to the SICAS capacity beginning with 2Q 2011 for comparison with prior quarters. 4Q 2011 IC capacity (including TSMC and UMC) was 2,205 thousand wafers, up 2.5% from 2,151 thousand in 3Q 2011 and the seventh consecutive quarterly increase. IC capacity in 4Q 2011 was just 1% below the record capacity of 2,223 thousand wafers in 3Q 2008 and was up 14% from the cyclical low of 1,927 thousand wafers in 3Q 2009.



The trend for MOS IC capacity utilization is shown in the chart below. The SICAS data on capacity utilization for MOS ICs excluding foundry wafers was used through 1Q 2011. This data series is fairly comparable to the 2Q-4Q 2011 SICAS total MOS IC capacity utilization which does not included TSMC and UMC. For the current cycle, utilization peaked at 94.9% in 2Q 2010. 4Q 2011 utilization dropped to 88.9%, the lowest level since 88.8% in 4Q 2009. The 4Q 2011 drop in utilization was expected due to the weak semiconductor market – primarily caused by floods in Thailand disrupting HDD production and economic weakness in Europe.




Capacity utilization will likely recover by 2Q 2012. Digitimes say industry sources expect TSMC’s 2Q 2012 utilization to be around 95% due to strong orders. Capacity growth in 1Q 2012 should be relatively flat. Combined data on semiconductor manufacturing equipment bookings and billings from SEMI and SEAJ shows billings have declined in each of the last three quarters, with 4Q 2011 down 24% from 1Q 2011. Bookings began to pick up in 4Q 2011, indicating capacity growth should resume by the second half of 2012. Year 2012 billings were $34 billion, up 8.8% from 2011. SEMI forecasts 18% growth in fab equipment spending in 2013.






 [post_title] => SICAS is dead (and WSTS isn't feeling too good) [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => sicas-is-dead-and-wsts-isnt-feeling-too-good [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:43:29 [post_modified_gmt] => 2019-06-15 02:43:29 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/sicas-is-dead-and-wsts-isnt-feeling-too-good.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 1105 [post_author] => 9491 [post_date] => 2012-03-13 14:24:00 [post_date_gmt] => 2012-03-13 14:24:00 [post_content] =>  There were three keynotes at CDNLive this morning, and one theme ran through them: collaboration. In fact there was one specific instance of collaboration that all three people mentioned. Taping out an ARM Cortex-A15 in TSMC 20nm technology using a Cadence tool flow.

Lip-Bu, Cadence's CEO, went first. He had some numbers showing that semiconductors and electronics should continue to grow at twice the rate of world GDP. And the GSA semiconductor index is all going up for the next couple of quarters. Underlying this growth is that increasing integration leads to many more devices. Mainframes shipped perhaps 1M units. PCs 100M units. But mobile internet (smartphone, iPad) are in the 10B unit range.

Rick Cassidy of TSMC was next up. He had an interesting retrospective on cost. From 1970 to today, transistor cost has reduced by 10[SUP]-8[/SUP] and microprocessor cost per transistor per cycle by 10[SUP]-11[/SUP]. An example Rick uses with MBA students (who know nothing about semiconductor) is that if Manhattan was a chip in 1962, by today it has shrunk so much that it fits in an iPod screen. And if we continue on the same path for another 50 years, the entire world will fit in that screen. Of course driving this is the scale of fabs like those TSMC is building. 180,000 12" wafers per month. Last year, TSMC shipped 13.2M 8" equivalent wafers. That's a lot of silicon.

Tom Lantzsch of ARM started by asking everyone whether they were more likely to return home if they had forgotten their wallet than their phone and most of us figured we could do more easily without our wallet. His interesting statistic of the day is that there is a need for approximately one server in the cloud for every 600 mobile phones (and, for every 120 or so tablets). ARM is increasingly moving into the home (smartTV) and the car (infotainment). Underlying everything ARM does is energy efficiency (aka low power). This is why ARM is moving into servers in a move that has many commentators perplexed. ARM's view is that servers will mimic what has happened in SoCs in smartphones, with a general purpose CPU (Intel) being replaced by multiple smaller CPUs and specialized functions such as video decode (of course, no prizes for guessing which CPUs Tom is expecting those to be). Developing countries simply don't have the power to build a datacenter the way they are currently done. Instead, he expects servers with a power budget of 5W such as the Calxeda one, simplifying not just power, but cabling and physical size. Servers are likely to be specialized since, for example, netflix doesn't need general purpose servers, just specialized video pumps.

Tom's equivalent of TSMC's wafer statistics were that ARM now has 275+ silicon partners, 900+ ecosystem partners, 30B+ ARM-based chips shipped. 50+ mobile phone application processors. 100+ phone designs. 100+ tablet designs (where are they all?), 1B+ applications. That's a lot of compute power.





 [post_title] => CDNLive: the Keynotes [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => cdnlive-the-keynotes [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:39:40 [post_modified_gmt] => 2019-06-15 01:39:40 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/cdnlive-the-keynotes.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 1104 [post_author] => 20367 [post_date] => 2012-03-13 11:25:00 [post_date_gmt] => 2012-03-13 11:25:00 [post_content] =>  After the introduction of the NEWiPAD, Apple has placed itself just two short steps away from dominating the computer market – including PCs. One step, which is widely reported, is a smaller iPAD with an 8” screen that aims for a $299 price point. Amazon will take the rest of the market under $299. The second step is purely speculation on my part but is within easy reach of the current hardware and will result in re-alignments in the semiconductor industry to the benefit of Apple and detriment of everyone else. A leveling will occur that forces some to return to their area of expertise, including a software company based in Redmond. The strategy is multi-faceted and thus will require an additional blog to fully outline.

To begin with we must recognize that the NewiPAD will not only reinforce but expand Apple’s lead in the tablet market. Tim Bajarin in his latest tech opinions column calls it revolutionary because of the impact the high-resolution screen will have on several industries. It is a great article that I highly recommend to anyone who follows the computer industry. After reading this, I sensed that Apple will not want to stop with what they have in the current iPAD but extend it further in order to make it even more competitive with respect to ultrabooks.

As a long time processor marketing guy, I see an opportunity for Apple to go one step further and that is to leverage the Retina display with a high performance graphics solution connected to its future A6 processor. For an additional $20-$25 of BOM cost, Apple can add an AMD or nVidia mobile graphics chip that will push the iPAD into a similar performance window as the ultrabooks to be powered by Intel’s Ivy Bridge – ULV parts. That’s because in this tablet, ultrabook market the Processor is not required to be high performance as the work-load shifts to the graphics unit. Thus the decision by Intel to spend the new transistor budget on improving the Ivy Bridge graphics unit.

The interesting dynamic that will play out in 2012 is that Intel’s Ivy Bridge ULV part will probably not drop below $225 for PC OEMs. Apple therefore will have the opportunity to introduce a $899-$999 Gamer iPAD with 4G LTE that has a $175 processor+graphics cost advantage. Furthermore, I can envision a Gamer iPAD with an 11” screen (same as MAC Air PC) that with an optional keyboard can find its way into the corporate market as an alternative to a Windows 8 machine running on an ARM based nVidia Tegra 3 or an Intel x86 based Atom processor. Apple then will leave it up to corporations to decide if they need an Intel Ivy Bridge based MAC Air or an A6 ARM based iPAD with PC level graphics selling at a discount but delivering higher margins to Apple.

In my previous blog, I mentioned how Apple’s Phil Schiller, Senior VP or Worldwide Marketing, stated that the new A5X processor with quad core graphics was 4 times faster than nVidia’s Tegra 3 and that nVidia resisted responding aggressively to the claims because they had other business at risk with Apple. The de-positioning of the Tegra 3 was a deliberate attempt by Apple to say to nVidia that they should abandon their tablet and smartphone attempts and return to their core, which is developing high-performance PC and supercomputing graphics solutions (In addition, Apple has effectively tagged competitive tablets as less than devices). With a Gamer Tablet, Apple will in effect force nVidia to choose between competing with them or cooperating, because the alternative is to let AMD take the business.

In the next blog we can look at Apple’s likely impact on Intel and Qualcomm in the coming year.

Full Disclosure: I am Long AAPL, INTC, QCOM and ALTR




 [post_title] => The Coming Gamer Tablet from...... Apple! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => the-coming-gamer-tablet-from-apple [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:43:27 [post_modified_gmt] => 2019-06-15 02:43:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/the-coming-gamer-tablet-from-apple.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 1103 [post_author] => 3 [post_date] => 2012-03-12 18:53:00 [post_date_gmt] => 2012-03-12 18:53:00 [post_content] => I love to read good news about growth in EDA especially when our industry has seen single-digit growth for several years now. What I read on March 8th from ClioSoft stated a 53% increase in bookings for 2011, now that's what I call growth.

ClioSoft provides Hardware Configuration Management (HCM) software to EDA users typically doing transistor-level IC design for both schematics and layout. I've been able to speak with several users of ClioSoft tools last year to find out first-hand what their experience was in adopting and using HCM in an IC design flow:


I blogged recently about, "What Just Changed on my Transistor-Level Schematic" and it's getting plenty of discussion both here at SemiWiki and on LinkedIn with some 1,261 page views at SemiWiki in under a month. Engineers are interested in how to manage their IC design projects better, especially as their team size grows and becomes geographically separated. [post_title] => More Growth in EDA [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => more-growth-in-eda [to_ping] => [pinged] => [post_modified] => 2012-03-12 18:53:00 [post_modified_gmt] => 2012-03-12 18:53:00 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/more-growth-in-eda.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 1102 [post_author] => 4 [post_date] => 2012-03-12 13:10:00 [post_date_gmt] => 2012-03-12 13:10:00 [post_content] => Designing larger than ever SoC, integrating multiple ARM’s Cortex-A15 and Cortex-A9 microprocessor cores as well as complexes IP functions like HDMI controller, DDR3 Memory controller, Ethernet, SATA or PCI Express controller are pushing designers to search for better price, performance and area tradeoffs and the SoC interconnect plays a vital role in serving this need. Using an advanced Network-on-Chip (NoC) like Arteris FlexNoC is an efficient solution to optimize the SoC and get the best possible return on the high investment linked with state of the art SoC development, by launching the IC in the right market window and benefit from a TTM advantage over the competition. Architects also want to virtually prototype their design, as it can be a good way to run these price, performance and area tradeoffs at early stages of the design, that they can do using Carbon’s SoCDesigner Plus, and prove their design assumptions before committing to the design implementation.





The joint Carbon/Arteris solution offers design teams a way to easily create and import accurate Arteris FlexNoC interconnect models for Carbon SoCDesigner Plus: the new Carbon/Arteris flow allows Carbon’s SoCDesigner Plus users to use Arteris FlexNoC to configure their NoC interconnect fabric IP and then upload the configuration to Carbon IP Exchange. The web portal then creates a 100% accurate virtual model of the configuration and makes it available for download and use in SoCDesigner Plus. “We see strong demand for models of Arteris’ NoC interconnect IP,” states Bill Neifert, chief technology officer at Carbon Design Systems®, the leading supplier of virtual platform and secure model solutions. “Our partnership with Arteris enables engineers to make architectural decisions and design tradeoffs based upon a 100%-accurate virtual representation.”





“Simulation with virtual models of our NoC interconnect IP are the best way to make system-on-chip architectural optimizations and tradeoffs,” comments Kurt Shuler, Arteris’ vice president of marketing. “By partnering with Carbon to make 100% accurate models of our IP available on Carbon IP Exchange, we are empowering design teams to utilize virtual models earlier in the design process.”

Going on Carbon IP Exchange web portal, we can see that the partnership allow to run a secured flow: the FlexNoC model is compiled directly from Arteris's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Carbon’s SoC Designer Plus virtual platform. There is no “interpretation”, no modeling task in between the RTL source code from Arteris and the virtual prototyping usage within Carbon SoCDesigner Plus.

To learn more about FlexNoC IP from Arteris availability in IP Exchange web portal from Carbon design Systems, just go here.

By Eric Esteve from IPNEST [post_title] => Virtual Prototype your SoC including FlexNoC [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => virtual-prototype-your-soc-including-flexnoc [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:43:27 [post_modified_gmt] => 2019-06-15 02:43:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/virtual-prototype-your-soc-including-flexnoc.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 1101 [post_author] => 3 [post_date] => 2012-03-12 11:01:00 [post_date_gmt] => 2012-03-12 11:01:00 [post_content] => I bought my first personal computer in 1979, it was a Radio Shack TRS-80 Model I with just 16KB of RAM, a BW monitor and casette tape for storage. The reason that I chose the Radio Shack over the Apple II was that it cost less, so I was always interested in Apple products and the engineers behind them since the early days. It was pure delight to read the autobiography of Steve Wozniak called iWoz, and the Kindle version costs only $8.61.



Wozniak writes in a style that sounds like he is having a conversation with you, face to face, very readable and personal. In the book he covers his family, upbringing, school days, pranks and how his father's job in engineering attracted him to also pursue an engineering career.

A fascination with science, math and building electronics projects set the stage for Steve Wozniak to meet the younger Steve Jobs and together they start building and selling illegal phone devices to make toll-free calls anywhere in the world. Wozniak does stints in college at Colorado and California, then lands a dream job at HP where he loves working on calculator designs. Part-time outside of HP he designs and builds the Apple I and Jobs sells the first 100 to a store for $50,000 to start their fledgling company.

In those early days an engineer like Wozniak would first design the computer system on paper, then breadboard the design with wire wrap, plug in chips, then start debugging it by using oscilloscopes or simply connecting the output to a TV. Very little software existed to simulate an actual design, so it was build first, then debug in hardware.

Wozniak hesitantly leaves HP to found Apple and the folks at HP simply let him go. They forgot to copyright the Apple 1 and soon there was an exact clone, so for the Apple II they didn't repeat that mistake. Engineering won out over marketing (Jobs) in the Apple II as Wozniak insisted that they give seven expansions slots, not just a measly two. It was interesting to read about how DRAM chips from Intel replaced SRAM in the Apple computer, how they choose their CPU, writing a dialect of BASIC, interfacing with the first 5 1/4 inch floppy drives, creating boot ROMs, etc. If you are a computer geek, then this story is for you.



The rate of growth of Apple and how its IPO made hundreds of millionaires is the stuff that drives risk takers of all sizes in Silicon Valley and around the world to build their own companies and try to change the world.


After the IPO at Apple Wozniak had a plane crash, recovered and then started to move in a different direction - like finishing up his fourth year of college under an assumed name, sponsor rock concerts and promote peace between the US and the Soviet Union.

Fame and fortune took a personal toll as Wozniak got divorced and then re-married. He talks about helping out his local school district by teaching a computer class, then venturing into charities and even funding the Tech Museum in San Jose.

In the 1980's I can remember visiting Apple Computer to sell them EDA software at a time when they were still designing their own graphics chips. When Steve Jobs saw the GUI on our EDA tool he said, "Well, that's just brain dead." Of course, he was right and now that EDA company is history.

If you are curious about the history of the Personal Computer and want to hear it straight from the engineer of the Apple I and Apple II, then get this book and enjoy the journey.


[post_title] => Book Review - iWoz [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => book-review-iwoz [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:43:25 [post_modified_gmt] => 2019-06-15 02:43:25 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/book-review-iwoz.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 1092 [post_author] => 28 [post_date] => 2012-03-11 19:00:00 [post_date_gmt] => 2012-03-11 19:00:00 [post_content] =>
As this blog is being posted I’m on my way to Dresden for the 2012 Design Automation and Test Conference. DATE used to bounce between Munich and Paris, I have attended many times but not in the past couple of years. No excuse really, just busy with other things.
DATE 2012 Highlights in Dresden include E-Mobility and More-than-Moore in the Conference and Ecosystem Exhibition. For me DATE 2012 holds three exciting things:


[LIST=1]
  • I have never been to Dresden
  • I will visit the GLOBALFOUNDRIES Fab 1

  • I will moderate a panel on the semiconductor ecosystem with executives from TSMC, GFI, and eSilicon


    Dresden has a long history and is one of the cultural, educational, political and economic centers of Germany. I will have some time to be a tourist so please suggest sites that I must see. The military museum is on my list and hopefully a beer garden or two. German beer and pretzels, I can’t wait! Also, a recommendation of the best local food would be greatly appreciated. I promise to fill my iPhone 4s with pictures for the trip report.

    The Fab 1 tour will be on Monday which includes lunch (I blog for food). It will be interesting to see the difference between state of the art Taiwan and German fabs.

    Monday evening will be the DATE reception (I blog for beer). I hope to see many friends and colleagues from around the world, it will be like a family reunion without the drama!

    Tuesday morning will be Mojy’s Keynote:

    Mojy Chian will give an outlook on the future development and role of foundries presenting "New Foundry Models - Accelerations in Transformations of the Semiconductor Industry", focusing on the new collaborative approach in technology development and high-end manufacturing. GLOBALFOUNDRIES is the first foundry with global footprint and leading edge manufacturing sites in Dresden, Germany, Singapore and the US.

    Tuesday lunch will be the session I’m moderating. Full disclosure, I’m replacing Malcolm Penn, Future Horizon’s CEO who was not able to make it. I’m happy to do it as my friend and former Virage Logic colleague Yervant Zorian is the organizer. Also, I’m very passionate about the future of the semiconductor ecosystem so it is a good job for me.

    2.1 EXECUTIVE SESSION: What Roles will the Foundries and Fabless Houses Play in Advanced Technology Nodes
    ?

    Date:
    Tuesday 13 March, 2012
    Time: 1130 - 1300
    Location / Room: Saal 5


    Executives:

    Douglas Pattullo, Director of Technology Support, TSMC, NL
    Yves Mathys, CEO, Abilis Systems, CH
    Gerd Teepe, Vice President, GLOBALFOUNDRIES, DE
    Robert Cadman, General Manager & Vice President, eSilicon, UK


    Moderator:

    Daniel Nenni, Founder, SemiWiki.com

    Organiser:

    Yervant Zorian, Synopsys, US

    The continuously technology scaling in advanced nodes can dramatically impact business performance of the semiconductor industry. It can also significantly affect the age-old COT flow, fabless design and pure play wafer manufacturing flow. The executives in this session will discuss future trends and upcoming changes in the semiconductor industry and their impact on the roles to be played by of the foundries, the fabless houses and the rest of the value chain.


    Tuesday afternoon I will spend time at the exhibition investigating what is new in the semiconductor ecosystem. Tuesday evening is a joint press talk with Synopsys & GLOBALFOUNDRIES:

    Antun Domic, Senior Vice President and General Manager, Implementation Group, Synopsys, and Mojy Chian, Senior Vice President Design Engineering, GLOBALFOUNDRIES, will talk about synergies and challenges with focus on 20 nm technology.

    Clearly my DATE 2012 trip report will be an interesting read so stay tuned to SemiWiki.com!






    [post_title] => My Design Automation and Test in Europe Conference Agenda (DATE 2012) [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => my-design-automation-and-test-in-europe-conference-agenda-date-2012 [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:43:24 [post_modified_gmt] => 2019-06-15 02:43:24 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/my-design-automation-and-test-in-europe-conference-agenda-date-2012.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 1100 [post_author] => 9491 [post_date] => 2012-03-10 16:24:00 [post_date_gmt] => 2012-03-10 16:24:00 [post_content] =>  Last month Brian Bailey at EDN moderated an interesting webinar about power issues. Unusually, it combined two different domains: doing things by modeling and actually taking measurements off real chips and boards. The two participants were Arvind Shanmugavel from the Apache subsidiary of Ansys, and Randy White from Tektronix.

    Nobody needs me to tell them that power is a major issue for chip and board design. This webinar wasn't so much about how to reduce power, important though that is, but more about how to deliver power and analyze what is being delivered, and then take measurements to see what is really happening. With low noise margins but a transistor threshold voltage that cannot change much, issues with the power supply such as voltage droop will cause systems to fail.

    One of the biggest areas is active state power management whereby the software works with the underlying chip to control things like voltage island and power down blocks. If a block doesn't need to produce its result fast then why bother to run it in high speed/high power mode. The challenge with this is that the transitions, changing the voltage of a block or powering it on or off produce major transients in the power network. The most extreme is power up a block that was powered down. Done naively the inrush current will cause the voltage to drop to the whole chip and so the received wisdom is to power the block up slowly (which, of course, means you know far enough in advance that you'll need it) and only connect the main power transistors when the block is up to the supply voltage (so no inrush current).

    For me the most interesting parts were Randy's comments about measuring everything since it's not an area I know lots about (I'm a software guy by background). At GHz performance levels, everything affects everything. Every probe has its own inductance, capacitance, resistance and so affects the measurement. I had no idea that Tektronix provides Spice models of all their probes so that you can work out what you expect to see on the scope given which probes you are using, since it differs from what the simulation says the actual signal value will be.

    Arvind had an interesting example showing how the thermal map of a die varies dependent on the package. And not just due to thermal aspects of the package but transient power supply effects too.

    We used to have a lot of margin on power supplies, with as much as 25% of tolerance. Now, especially in battery powered mobile devices it can be as low as 5%. This requires both an accurate power model and accurate ways of taking measurements off the actual devices without, Heisenberg style, perturbing the actual system too much.

    The webinar is here.




     [post_title] => Power Issues for Chip and Board: webinar [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => power-issues-for-chip-and-board-webinar [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:55:27 [post_modified_gmt] => 2019-06-15 01:55:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/power-issues-for-chip-and-board-webinar.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 1095 [post_author] => 9491 [post_date] => 2012-03-10 09:00:00 [post_date_gmt] => 2012-03-10 09:00:00 [post_content] =>  Next Wednesday is the Common Platform Technology Forum. "Common Platform" is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and Global Foundries. Although they have many partners, historically they have worked closely with ARM and Synopsys.

    TD versus capital has gone through a couple of phases. It used to be that anyone could build a fab but getting a process to run in it was expensive. Then in the 90s, fabs suddenly became really expensive and the cost of licensing a process was a lot less. But then TD got really hard again, and it became so expensive that only Intel could really afford to go it completely alone. Hence alliances like the Common Platform.

    Wednesday March 14th at the Santa Clara Convention Center is this years Common Platform Technology Forum. The keynote speakers (from 9am to 11.30am) are:


    • Dr. Gary Patton, Vice President of Semiconductor Research & Development Center, IBM
    • Gregg Bartlett, Chief Technology Officer, GLOBALFOUNDRIES
    • Dr. Jong Shik Yoon, Senior Vice President of Semiconductor R&D, Samsung
    • Simon Segars, Executive Vice President and General Manager, Physical IP Division, ARM


    There is a partner pavilion then open for the rest of the day. I'm presuming lunch is provided there too. And since it is Pi day (3.14), from 1.30pm they will be serving...wait for it...specialty pies.

    From 1-2pm is a panel session on the R&D pipeline for future technology innovation. There are representatives of (surprise) Global Foundries, Samsung and IBM. Along with ARM and the College of Nanoscale Science and Engineering (which I confess to never having heard of).

    In the afternoon are presentations from Synopsys, Cadence and Mentor (how's that for EDA neutrality?).

    At 2pm, John Chilton of Synopsys talks about designing ARM-based SoCs at 28nm and 20nm. He is followed, at 3pm, by Sampta Bansal of Cadence, who sees Synopsys's 20nm and raises it by talking about delivering on 20nm and embarking on 14nm. Then, at 4pm, Mentor's Michael White talks about double patterning at 20nm.

    For me the Mentor presentation looks the most interesting since it looks like a sort of introduction to double patterning, a subject that I need to learn a lot more about. And so, probably, do you. To register click on the banner below.




     [post_title] => Common Platform Technology Forum: Peering into the Future [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => common-platform-technology-forum-peering-into-the-future [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:39:38 [post_modified_gmt] => 2019-06-15 01:39:38 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/common-platform-technology-forum-peering-into-the-future.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 1094 [post_author] => 9491 [post_date] => 2012-03-09 14:17:00 [post_date_gmt] => 2012-03-09 14:17:00 [post_content] =>  Last week, the Japanese memory company Elpida filed for bankruptcy. There is worldwide overcapacity in DRAM and somebody had to go. Its strength and the weakness was that it was much more outward facing than most of the Japanese semiconductor and electronic industry. So it had to compete globally and wasn't up to the task.

    I think looking at the Japanese mobile phone industry is revealing. If you visit Japan you get some idea of the problem. Everything is too inward looking. All the mobile phones are great and seem in some ways to be ahead of what we have in the US, and they are all made by Japanese manufacturers. But that is the problem, they are made by manufacturers who have given up in the rest of the world.

    Greg Hinckley, the COO of Mentor Graphics, once told me about interviewing a candidate for a finance position who came from American Airlines. Their focus, the candidate said, was to touch down 30 seconds ahead of United. It was as if Southwest and Jet Blue and all the rest didn’t even exist. Being the best airline just meant being the best legacy airline: beat United, Delta and the others.

    The Japanese cell-phone companies are like that. They are so competitive for their share of the Japanese market that they have given up on the global market and what it takes to compete there. Of course, the Japanese cell-phone transmission standards are different which means that you have to decide whether to compete in Japan, overseas or both. Those different standards may have looked like a giving a good unfair advantage to the Japanese since Nokia, Ericsson or Samsung were unlikely to focus on the Japanese standard first even during the initial high-growth period. But on the other hand the Japanese manufacturers have no market share in the rest of the world, which is orders of magnitude bigger.

    Last time I visited the usual Japanese semiconductor companies I got the feeling that they were all only competing with each other. By and large they were making chips to go into consumer electronics products for the Japanese market. There were obviously far more products and far more chips being done than could possibly make money, just like all those cell-phones and cell-phone chips couldn’t be making money (not to mention that the Japanese market is already saturated).

    With too many companies, and too many uncompetitive semiconductor divisions, consolidation is to be expected. But Japanese politics is inward facing too and so they can only merge with each other and gradually move towards what I call Japan Inc in the semiconductor world (to be fair, this same issue is one that affects my American Airlines example; British Airways or Lufthansa is simply not allowed to buy a major stake, recapitalize them and clean them up because congress has laws preventing it).

    I said a couple of years ago: "So it looks like gradually the semiconductor companies will consolidate into a memory company (Elpida) and a logic company and, based on past history, they won’t take the hard decisions necessary to be competitive globally rather than just in Japan."

    Well, it didn't work out too well in memory, although presumably Elpida will re-emerge in some form.

    On the logic side, NEC/Renasas(Hitachi/Mitsubishi), Fujutsu and Panasonic are rumored to be in discussions to merge. Toshiba is not on the list since it seems to be strong enough to go it alone, at least for now. But as fabs get bigger, and the cost of an individual design gets bigger, you can only make money addressing large global markets, not supplying a fragmented domestic market. Based on past form, merging Mitsubishi and Hitachi to form Renasas, and before they had finished getting that sorted out, adding them into NEC, and before that was done throwing in Fujitsu and Panasonic...let's come back in a year or two and see how that's working.

    I guess I'll stick with my statement from a couple of years ago. It's still looking good.




     [post_title] => Elpida and Japan Inc [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => elpida-and-japan-inc [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:43:23 [post_modified_gmt] => 2019-06-15 02:43:23 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/elpida-and-japan-inc.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 1106 [post_author] => 12 [post_date] => 2012-03-13 20:16:00 [post_date_gmt] => 2012-03-13 20:16:00 [post_content] => The SICAS (Semiconductor Industry Capacity Statistics) program has been discontinued after the release of the 4Q 2011 data, available through the SIA at http://www.sia-online.org/industry-statistics/semiconductor-capacity-utilization-sicas-reports/

    The latest report stated: “Due to significant changes in the SICAS program participation base in 2011, the quarterly SICAS capacity and utilization report will be discontinued, effective Quarter 1 2012.” SICAS lost the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) and United Microelectronics Corporation (UMC) beginning in 2Q 2011. SICAS members likely questioned the value of continued participation without the two largest wafer foundry companies.

    The end of SICAS is a major disappointment. The semiconductor industry has lost the definitive source of capacity and utilization data, a key component in determining the current and near term industry conditions. It is especially disappointing to me since I served on the founding executive committee of SICAS in 1995.

    The death of SICAS follows the withdrawal of Intel and Advanced Micro Devices (AMD) from World Semiconductor Trade Statistics (WSTS) as originally reported in the Wall Street Journal: http://www.djnewsplus.com/rssarticle/SB133045771410082239.html
    Without Intel and AMD, it will be extremely difficult for WSTS to report accurate statistics for microprocessors. Intel and AMD account for over 90% of the microprocessor market and microprocessors account for about 15% of the semiconductor market. WSTS may need to drop microprocessors from its product coverage, which would result in WSTS no longer being a reliable source of data on the overall semiconductor market.

    As with the loss of SICAS, the loss of Intel and AMD in WSTS is a significant disappointment. I was Texas Instrument’s representative to WSTS for 14 years and served a term as WSTS chairperson. However I believe WSTS will adapt and survive. The organization provides detail on numerous product and application markets which provide vital information to member companies and industry analysts.

    Final SICAS data


    The chart below shows SICAS data for total IC capacity in thousands of eight-inch equivalent wafers per week. Capacity for TSMC and UMC was added to the SICAS capacity beginning with 2Q 2011 for comparison with prior quarters. 4Q 2011 IC capacity (including TSMC and UMC) was 2,205 thousand wafers, up 2.5% from 2,151 thousand in 3Q 2011 and the seventh consecutive quarterly increase. IC capacity in 4Q 2011 was just 1% below the record capacity of 2,223 thousand wafers in 3Q 2008 and was up 14% from the cyclical low of 1,927 thousand wafers in 3Q 2009.



    The trend for MOS IC capacity utilization is shown in the chart below. The SICAS data on capacity utilization for MOS ICs excluding foundry wafers was used through 1Q 2011. This data series is fairly comparable to the 2Q-4Q 2011 SICAS total MOS IC capacity utilization which does not included TSMC and UMC. For the current cycle, utilization peaked at 94.9% in 2Q 2010. 4Q 2011 utilization dropped to 88.9%, the lowest level since 88.8% in 4Q 2009. The 4Q 2011 drop in utilization was expected due to the weak semiconductor market – primarily caused by floods in Thailand disrupting HDD production and economic weakness in Europe.




    Capacity utilization will likely recover by 2Q 2012. Digitimes say industry sources expect TSMC’s 2Q 2012 utilization to be around 95% due to strong orders. Capacity growth in 1Q 2012 should be relatively flat. Combined data on semiconductor manufacturing equipment bookings and billings from SEMI and SEAJ shows billings have declined in each of the last three quarters, with 4Q 2011 down 24% from 1Q 2011. Bookings began to pick up in 4Q 2011, indicating capacity growth should resume by the second half of 2012. Year 2012 billings were $34 billion, up 8.8% from 2011. SEMI forecasts 18% growth in fab equipment spending in 2013.






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  • SICAS is dead (and WSTS isn’t feeling too good)

    SICAS is dead (and WSTS isn’t feeling too good)
    by Bill Jewell on 03-13-2012 at 8:16 pm

    The SICAS (Semiconductor Industry Capacity Statistics) program has been discontinued after the release of the 4Q 2011 data, available through the SIA at http://www.sia-online.org/industry-statistics/semiconductor-capacity-utilization-sicas-reports/

    The latest report stated: “Due to significant changes in the… Read More


    CDNLive: the Keynotes

    CDNLive: the Keynotes
    by Paul McLellan on 03-13-2012 at 2:24 pm

    There were three keynotes at CDNLive this morning, and one theme ran through them: collaboration. In fact there was one specific instance of collaboration that all three people mentioned. Taping out an ARM Cortex-A15 in TSMC 20nm technology using a Cadence tool flow.

    Lip-Bu, Cadence’s CEO, went first. He had some numbers… Read More


    The Coming Gamer Tablet from…… Apple!

    The Coming Gamer Tablet from…… Apple!
    by Ed McKernan on 03-13-2012 at 11:25 am

    After the introduction of the NEWiPAD, Apple has placed itself just two short steps away from dominating the computer market – including PCs. One step, which is widely reported, is a smaller iPAD with an 8” screen that aims for a $299 price point. Amazon will take the rest of the market under $299. The second step is purely speculation… Read More


    More Growth in EDA

    More Growth in EDA
    by Daniel Payne on 03-12-2012 at 6:53 pm

    I love to read good news about growth in EDA especially when our industry has seen single-digit growth for several years now. What I read on March 8th from ClioSoft stated a 53% increase in bookings for 2011, now that’s what I call growth.

    ClioSoft provides Hardware Configuration Management (HCM) software to EDA users typically… Read More


    Virtual Prototype your SoC including FlexNoC

    Virtual Prototype your SoC including FlexNoC
    by Eric Esteve on 03-12-2012 at 1:10 pm

    Designing larger than ever SoC, integrating multiple ARM’s Cortex-A15 and Cortex-A9 microprocessor cores as well as complexes IP functions like HDMI controller, DDR3 Memory controller, Ethernet, SATA or PCI Express controller are pushing designers to search for better price, performance and area tradeoffs and the SoC interconnect… Read More


    Book Review – iWoz

    Book Review – iWoz
    by Daniel Payne on 03-12-2012 at 11:01 am

    I bought my first personal computer in 1979, it was a Radio Shack TRS-80 Model I with just 16KB of RAM, a BW monitor and casette tape for storage. The reason that I chose the Radio Shack over the Apple II was that it cost less, so I was always interested in Apple products and the engineers behind them since the early days. It was pure delight… Read More


    My Design Automation and Test in Europe Conference Agenda (DATE 2012)

    My Design Automation and Test in Europe Conference Agenda (DATE 2012)
    by Daniel Nenni on 03-11-2012 at 7:00 pm


    As this blog is being posted I’m on my way to Dresden for the 2012 Design Automation and Test Conference. DATE used to bounce between Munich and Paris, I have attended many times but not in the past couple of years. No excuse really, just busy with other things.
    DATE 2012 Highlights in Dresden include E-Mobility and More-than-Moore… Read More


    Power Issues for Chip and Board: webinar

    Power Issues for Chip and Board: webinar
    by Paul McLellan on 03-10-2012 at 4:24 pm

    Last month Brian Bailey at EDN moderated an interesting webinar about power issues. Unusually, it combined two different domains: doing things by modeling and actually taking measurements off real chips and boards. The two participants were Arvind Shanmugavel from the Apache subsidiary of Ansys, and Randy White from Tektronix.… Read More


    Common Platform Technology Forum: Peering into the Future

    Common Platform Technology Forum: Peering into the Future
    by Paul McLellan on 03-10-2012 at 9:00 am

    Next Wednesday is the Common Platform Technology Forum. “Common Platform” is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and… Read More


    Elpida and Japan Inc

    Elpida and Japan Inc
    by Paul McLellan on 03-09-2012 at 2:17 pm

    Last week, the Japanese memory company Elpida filed for bankruptcy. There is worldwide overcapacity in DRAM and somebody had to go. Its strength and the weakness was that it was much more outward facing than most of the Japanese semiconductor and electronic industry. So it had to compete globally and wasn’t up to the task.… Read More