About 13 months ago, the leak blogs posted news of “Artemis” on an alleged ARM roadmap slide, supposedly a new 16FF ARM core positioned as the presumptive successor to the Cortex-A57. Now, we’re finding out what “Artemis” may actually be, inside a multi-core PPA test chip on TSMC 10FinFET.… Read More
Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMCAt the recent TSMC Technology Symposium 2026, Siemens…Read More
PQShield unveils ultra-small PQC embedded security breakthroughs at Embedded World 2026As the threat of quantum computing to modern…Read More
Closing the Silicon Realization Gap: From Static DFM to Governance for Lifecycle (GFL)The semiconductor industry has achieved extraordinary mastery in…Read More
imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scalingimec announced that IC-Link by imec has joined…Read More
Who protects power protection chips?
Power protection chips are widely used these days to protect sensitive circuitry from over-voltage and over-current stress. However, these workhorse chips are often subjected to extraordinary thermal stress themselves and need to be protected from burning up – literally.
Power protection chips work like electronic fuses,… Read More
IMEC Technology Forum (ITF) – IC Innovation
IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.
Luc Van Den Hove is the president and CEO of IMEC and he… Read More
TSMC Leads Again with 3-D Packaging!
Continuing to find new ways to extend Moore’s Law, the foundry and technology leader is ready to show off its wafer level system integration prowess with two scalable platforms targeting key growth markets.
CoWoS® (Chip-On-Wafer-On-Substrate) goes after high-performance applications, providing the highest bandwidth and… Read More
Autotalks’ New V2X Processor Integrates CEVA-XC DSP to Support IEEE802.11p and WiFi
V2X stands for Vehicle to Everything and to be specific, V2X technology connects vehicles to other vehicles (V2V), infrastructure (V2I), motorcycles (V2M) and pedestrians (V2P) within wireless range for safety and mobility applications. If you consider that the US Department of transportation (USDOT) is expected to publish… Read More
5G, Video and SDNs – High Volume Drivers for Photonic Systems-on-Chip (PSoC)
The move towards 5G networks with demands for decreased latency ( 100 devices/m[SUP]2[/SUP]), and the desire to flexibly configure and integrate mobile, fixed, optical and satellite telecommunications is putting tremendous pressure on the design of next generation telecom equipment. Silicon photonics promises to be the… Read More
5G, Video and SDNs – High Volume Drivers for Photonic Systems-on-Chip (PSoC)
The move towards 5G networks with demands for decreased latency ( 100 devices/m[SUP]2[/SUP]), and the desire to flexibly configure and integrate mobile, fixed, optical and satellite telecommunications is putting tremendous pressure on the design of next generation telecom equipment. Silicon photonics promises to be the… Read More
Testing IGBTs before they go into EVs
In the pages of SemiWiki, we are usually talking about what to do with billions of really small transistors – for a change of pace today, we’ll discuss what to do with a few really big ones. Mentor Graphics has just announced their latest MicReD platform for thermal testing of IGBTs, experiencing a resurgence (pun intended) thanks… Read More
What Does an MPW and a Pizza Have in Common?
Design starts are critical to the growth of the semiconductor industry so enabling them is a common theme on SemiWiki. One thing we have not covered in detail is multi-project wafer services (MPW) which is the equivalent of ride sharing through the initial mask and wafer process. Larger semiconductor companies already do this … Read More
"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis
A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More
ASML High-NA EUV is Not Ready for High-Volume Production