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Moore’s law limitations and gravitational collapse at lower process nodes

Moore’s law limitations and gravitational collapse at lower process nodes
by Vaibbhav Taraate on 10-05-2015 at 4:00 pm

As stated in my previous article, about the complexity of the SOC with billions of transistors. It is essential to consider the real practical scenario for the two dimensional verses three dimensional structure of the chip. Although the new technological changes and evolution for the shrinking process node can create ease for… Read More


Solidly Across the Chasm

Solidly Across the Chasm
by Paul McLellan on 10-05-2015 at 12:00 pm

Last week I wrote about EDA companies crossing the chasm, with Jim Hogan (who needs no introduction) and Amit Gupta, CEO of Solido. So how did those rules work out for Solido?

See also Getting EDA Across the Chasm: 15 Rules Before and 5 After

The founding team of Solido:

  • discovered process variation for analog was a problem as companies
Read More

What NoCs with virtual channels really do for SoCs

What NoCs with virtual channels really do for SoCs
by Don Dingee on 10-05-2015 at 7:00 am

Most of us understand the basic concept of a virtual channel: mapping multiple channels of traffic, possibly of mixed priority, to a single physical link. Where priority varies, quality of service (QoS) settings can help ensure higher priority traffic flows unimpeded. SoC designers can capture the benefits of virtual channels… Read More


Something Old, Something New…EDA and Verification

Something Old, Something New…EDA and Verification
by Ellie Burns on 10-04-2015 at 12:00 pm

When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should … Read More


Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes

Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes
by Pawan Fangaria on 10-04-2015 at 7:00 am

There was a time when design goals were decided in the beginning, targeted on a particular technology node, design planning done for the same, and implementation done through point tools connected indesign flows customized according to the design. It’s no longer the case for modern SoC designs; there are multiple technology … Read More


TSMC Award Recognizes Andes’ IoT Credentials

TSMC Award Recognizes Andes’ IoT Credentials
by Majeed Ahmad on 10-03-2015 at 7:00 am

The system-on-chip (SoC) movement is intrinsically linked to external IP products, and here, it’s not just fabless chipmakers who work closely with IP suppliers. Large foundries like TSMC also maintain close relationships with IP vendors to optimize their process nodes and libraries for processor cores and other design… Read More


What’s Testing Design Limits at ITC?

What’s Testing Design Limits at ITC?
by Beth Martin on 10-02-2015 at 12:00 pm

The 46[SUP]th[/SUP] IEEE International Test Conference (ITC) will be held the week of October 5, 2015 at the Disneyland Hotel Conference Center in Anaheim, California. ITC is where you will discover the latest ideas and learn about practical applications of test technologies.

As you take in panels, tutorials, presentations,… Read More


Getting EDA Across the Chasm: 15 Rules Before and 5 After

Getting EDA Across the Chasm: 15 Rules Before and 5 After
by Paul McLellan on 10-02-2015 at 7:00 am

Crossing the Chasm by Geoffrey Moore (not that G. Moore!) is one of the most well known books on high technology marketing. When I worked at VaST, Mohr Davidow Ventures (MDV) invested in us and Moore (not Mohr), who was a partner there, spent an afternoon with us brainstorming what it would take for us to cross the chasm. Coincidentally,… Read More


Top 10 Reasons to invest in Interactive Design Rule Checking tools

Top 10 Reasons to invest in Interactive Design Rule Checking tools
by Tom Dillinger on 10-01-2015 at 12:00 pm

One of the most energetic presentations at the recent TSMC OIP 2015 symposium was given by Tom Williams from Qualcomm, who shared his insights (and enthusiasm!) for Mentor’s Calibre RealTime interactive Design Rule Checking (iDRC) product.

Paraphrasing Tom’s presentation (and with a tip of the hat to David Letterman), here … Read More


EDA By the Numbers, Phil Kaufman, Emerging Companies and More

EDA By the Numbers, Phil Kaufman, Emerging Companies and More
by Paul McLellan on 10-01-2015 at 7:00 am

The quarterly numbers are out from the EDAC Market Statistics Service (MSS) for Q2. The headline number is that revenue for the industry increased by 8.5% for Q2 to $1906.5M versus $1759.9M in Q2 last year. The four quarter moving average, that smooths out a lot of seasonality by comparing the most recent four quarters to the prior… Read More