TSMC is having an interesting year for sure. I was at the TSMC Symposium in Hsinchu last week and everyone was talking about the new 16FFC process. Silicon is out and it is exceeding expectations leading some people (me included) to believe that TSMC 16FFC will be the next TSMC 28nm in regards to popularity. To be clear, 16FFC is currently the “BEST” process node in regards to PPPA (price, performance, power, and area) available today, absolutely.
The proof is in the pudding of course and that pudding will arrive via the iPhone 7 this fall and yes, I am buying an iPhone 7 Pro to match my iPad Pro which I use every day. Netflixing on an iPad Pro at 30,000+ feet, priceless! It should have a “TSMC Inside” sticker on it for sure.
Speaking of FinFETs, we have published 64 FinFET related blogs thus far starting with Tom Dillinger’s three part Introduction to FinFET Technology series. The total views for the SemiWiki FinFET blogs exceeds 500k which is a lot of reading. FinFET blogs also have low bounce rates and high time-on-page numbers which means they are very engaging. Designing with FinFETs is still a hot topic so there are certainly more blogs to come.
At DAC, TSMC pioneered the partner theater allowing the fabless semiconductor ecosystem to shine, and this year it will be no different. You can see the latest TSMC Theater schedule HERE. If you are looking for me on the DAC exhibit floor that would be a good place to start. Or wherever there is free food.
Speaking of free food, TSMC is also very busy with other DAC activities that should be of interest. You can see the agenda HERE and please note that it includes breakfast, lunch, and dinner presentations so you can also find me there enjoying the free food.
As a pre #53DAC “Designing with FinFET” primer you should catch the TSMC and Solido Collaborate for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes webinar on Wed, June 1st, 2016 10:00 AM – 11:00 AM PDT. If the time does not work for you, sign up anyway and they will send you a link to the replay:
“Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule.
This webinar will discuss how TSMC and Solido collaborate to offer variation-aware design techniques for memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.”
And don’t forget that SemiWiki will again be hosting a DAC Networking reception on Wednesday night from 6:00pm to 7:00pm in the Trinity Street Foyer. This year we will be giving away copies of our new book “Prototypical”. My beautiful wife and I hope to see you there!