High-level synthesis (HLS) involves the generation of an RTL hardware model from a C/C++/SystemC description. The C code is typically referred to as abehavioraloralgorithmicmodel. The C language constructs and semantics available to architects enable efficient and concise coding – the code itself is smaller, easier to write/read,… Read More




Xilinx is Killing Altera!
At a recent outing with FPGA friends from days gone by, the long running Xilinx vs Altera debate has come to an end. The bottom line is that Xilinx has used the FUD (fear, uncertainty, and doubt) of the Intel acquisition quite effectively against Altera and is racking up 20nm and 16nm design wins at an alarming rate. It will be a while … Read More
ARM vs Intel: The New War Frontiers
With Intel’s exit from smartphone processor market, the competitive zones are redefined with its rivalry with ARM. Is ARM’s domination the only reason for Intel’s exit? With no competing architecture, is ARM a monopoly in smartphone processor IP market? What are the new areas of competition between ARM and Intel? I will attempt… Read More
It’s Time to Put Your Spice Netlists on a Diet
Spice circuit simulation remains the backbone of IC design validation. Digital cell library developers rely upon Spice for circuit characterization, to provide the data for Liberty models. Memory IP designers utilize additional Spice features to perform statistical sampling. Analog and I/O interface designers extend these… Read More
The amazing artificial intelligence we were promised is coming, finally
We have been hearing predictions for decades of a takeover of the world by artificial intelligence. In 1957, Herbert A. Simon predicted that within 10 years a digital computer would be the world’s chess champion. That didn’t happen until 1996. And despite Marvin Minsky’s 1970 prediction that “in from three to eight years we will… Read More
Network generator embeds TensorFlow, more CNNs
Research on deep learning and convolutional neural networks (CNNs) is on the rise – and embedding new algorithms is drawing more attention. At CVPR 2016, CEVA is launching their 2[SUP]nd[/SUP] generation Deep Neural Network (CDNN2) software with new support for Google TensorFlow.… Read More
Two New Announcements from Tanner EDA at #53DAC
Most mergers and acquisitions in the EDA world simply don’t work out financially a year or two after the deal is done, however I was pleasantly surprised to learn that Tanner EDA is doing quite well at #53DAC this year after the acquisition by Mentor Graphics back in March 2015. Everyone that I’ve been meeting with at … Read More
eSilicon Offers Free Semiconductor IP For Universities!
It is easy to forget the importance of academia’s role in the semiconductor ecosystem but it is important not to. If you look at the DNA of the semiconductor industry you will see how dependent we are on academic research for innovation and the necessary disruption that keeps us all gainfully employed. FinFETs are the first things… Read More
Whose IoT devices were breached in 2015?
IoT, as we all know, is not without issues–though we have become reliant upon it in many ways.. In 2015, there were some very viable and tangible proofs that the IoT field is fraught with real peril and that we as IoT designers, developers and companies need to be paying more attention to security. Just how many different IoT … Read More
Getting Maximum Performance Bang for Your Buck through Parallelism
Finding a way to optimally parallelize linear code for multi-processor platforms has been a holy grail of computer science for many years. The challenge is that we think linearly and design algorithms in the same way, but then want to speed up our analysis by adding parallelism to the algorithms we have already designed.
But the … Read More
Musk’s new job as Samsung Fab Manager – Can he disrupt chip making? Intel outside