There are a lot of clever techniques to automatically find and even implement methods for register gating and memory gating, but the bulk of power-saving still depends on designer and architect insight based on expected range of use of a device, complemented by practical use-case simulations. Of course this team needs to be able to see total power and breakdowns by type (switching, leakage, etc.) and by regions in the design in order to understand what areas need help and what fixes might provide the most useful reductions.
This Webinar is on September 27[SUP]th[/SUP] at 9am Pacific. Register now!
The design teams needs to be able to experiment quickly with possible power-saving options to see which might have the most significant impact. This requires the ability to run through a lot of experiments in a short time to compare and contrast options, especially since some options will have performance, area or latency impact. Obvious experiments include:
- Changing the Vt mix to reduce leakage in a block which is not very performance-sensitive
- Adding power-switching or DVFS to a block which use-cases show can handle the latency incurred in powering back on, or the reduction in performance at lower V/f.
- Adding higher-level clock gating to power down more logic in inactive modes.
- Adding gating to data and address ports on memories from which a surprising level of power savings can be milked by judicious gating of address and data busses.
These experiments can show significant opportunities for power saving but are generally too complex to be proved formally. That’s why these decisions generally require design judgment based on a broad sampling of simulation use-cases and what the design team believes should bound normal usage. That said, I know at least some design teams will make these fixes and also also build in software-controlled bail-out options to selectively disable gating if “normal” usage at a customer proves to exceed the bounds they expected 😎
The central value of a solution like this is sufficiently accurate power-estimation (within 15% of gate-level estimates), good visualization of power distributed by types, location in the design and some granularity in time, and fast-turn to get delta improvements based on what-if choices in the design architecture.
Power consumption impacts multiple applications and markets such as handheld, workstations, and servers to name a few. Because the greatest opportunities for optimizing power are at the micro-architecture and RTL design stages, the PowerPro Platform provides an interactive approach to power exploration and power reduction at RTL. This platform uses an unique architecture that eliminates iterations through simulation and synthesis, giving immediate power feedback.This web seminar will show how PowerPro easily identifies where power is wasted; from the micro-architectural level to memory, register and combinational elements. The platform provides “what-if” analysis, interactively assessing the impact on power due to potential design transformations.
What You Will Learn
· Survey results: Power reduction- who is doing it and when
· Overview of the PowerPro platform
· Interactive RTL analysis and exploration environment
· 3 detailled examples of RTL power reduction guidance
· Optimizing further with design exploration
· Examples and customer results
ABOUT THE PRESENTER
Before re-joining Mentor Graphics in 2015, Stuart managed the North American FAE team for Calypto Design Systems. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.
Who Should Attend
· RTL designers
· Power architects
· Project managers
· PowerPro RTL Low-Power
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