There are 3 common misconceptions about debugging FPGA with the real hardware:
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What are you ready to mobilize for FPGA debug?
Analog Bits Targets the Power Challenge at the Heart of Next-Generation ChipsAnalog Bits is expanding its role in advanced…Read More
Broadcom’s AI Engine Shifts Into OverdriveBroadcom’s fiscal third-quarter 2026 results show how artificial-intelligence…Read More
TSMC’s CoWoS Capacity to Double by 2028—and Rivals Will Still Win OrdersTSMC reportedly plans to double its Chip-on-Wafer-on-Substrate capacity…Read More
The Invisible Bottleneck Is Costing You Time You Can't Get BackBy Joel Jorgensen, FlowAccel. The 2026 Siemens EDA…Read More
RISC-V Business
I was at the 7[SUP]th[/SUP] RISC-V Workshop for two days this week. It was hosted by Western Digital at their headquarters in Milpitas. If you have not been following RISC-V, it is an open source Instruction Set Architecture (ISA) for processor design. The initiative started at Berkeley, and has been catching on like wildfire. … Read More
IP-SoC 2017: IP Innovation, Foundries, Low Power and Security
The 20[SUP]th[/SUP] IP-SoC conference will be held in Grenoble, France, on December 6-7, 2017. IP-SoC is not just a marketing fest, it’s the unique IP centric conference, with presentations reflecting the complete IP ecosystem: IP suppliers, foundries, industry trends and applications, with a focus on automotive. It will … Read More
Making Your Next Chip Self-Aware
One holy grail of AI software developers is to create a system that is self-aware, or sentient. A less lofty goal than sentient AI is for chip designers to know how each specific chip responds to Process variations, Voltage levels and Temperature changes. If a design engineer knew exactly which process corner that each chip was fabricated… Read More
Hierarchy Applied to Semiconductor IP Reuse
When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More
A Crossover MCU
Back in the day we had processors which consolidated computing power onto a chip, and out of these sprang (if you’ll excuse the Biblical imagery) microcontrollers (MCUs) in one direction and increasingly complex system-on-chip (SoC) processors in another direction. SoCs are used everywhere today, in smartphones, many IoT … Read More
Multi-Channel Multi Rate FEC Engine Webinar with Open Silicon
I will be pleased to moderate on December 7[SUP]th[/SUP] the Open-Silicon webinar addressing the benefits of the multi-channel multi-rate forward error correction (MCMR FEC) IP and the role it plays in high-bandwidth networking applications, especially those where the bit error rate is very high, such as high speed SerDes … Read More
Outsourced Operations: Reduced Risk, Fast Ramp, and Managed Complexity
One of the more interesting semiconductor success stories is Apple and how they transformed from a struggling computer company to a dominant chip maker. We covered this story in quite a bit of detail in our book “Mobile Unleashed” in Chapter 7 “From Cupertino” but the short answer to how they did it is: Outsourced Operations.
Apple’s… Read More
Field-Solver Parasitic Extraction Goes Mainstream
Layout parasitic extraction (LPE) has three primary goals – accuracy, capacity, and throughput. Traditionally, LPE tools have offered two methods for capacitance derivation, with tradeoffs on these goals:… Read More
CEVA and Local AI Smarts
When we first started talking about “smart”, as in smart cars, smart homes, smart cities and the like, our usage of “smart” was arguably over-generous. What we really meant was that these aspects of our daily lives were becoming more computerized and connected. Not to say those directions weren’t useful and exciting, but we weren’t… Read More
Why ASML Is Racing to Build 110 EUV Machines