The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node SurvivalThe philosophy of relying on a single, unified…Read More
CTO Interview with Taylor Barton of Certus SemiconductorTaylor Barton is a Lead Analog/Mixed-Signal and I/O…Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity By Defacto Staff Today’s chips are no longer…Read More
Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in ComputingThe Global Semiconductor Alliance will present Micron Technology…Read More
Auto makers have long relied on security by obscurity to get away with not defining or adhering to proper cyber security hygiene. This rationalization had been embraced in the context of low levels of automotive hacking mainly carried out by enthusiasts or so-called “white hat” or ethical hackers.
A new report from Strategy Analytics,… Read More
When we were first introduced to earbuds, in-ear speakers connected through thin wires to your phone (and earlier portable music devices), they seemed pretty convenient for private entertainment at work, while walking, exercising, doing almost anything. Until we started to realize those long dangly wires weren’t ideal. They’d… Read More
Semiconductor IP is one of the more exciting and most viewed topics we cover on SemiWiki, it has been that way since we began in 2011 and that trend will continue indefinitely, my opinion.
Semiconductor IP: Total Blogs: 640: Total Views: 3253751: Average: 5084
Based on the design starts we track, Cloud Computing is a leading semiconductor… Read More
One of the challenges in the RISC-V bid for world domination may be security. That may seem like a silly statement, given that security weaknesses are invariably a function of implementation and RISC-V doesn’t define implementation, only the instruction-set architecture (ISA). But bear with me. RISC-V success depends heavily… Read More
I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse… Read More
A Chinese scientist from a university in Shenzhen claims he has succeeded in creating the world’s first genetically edited babies. He told the Associated Press that twin girls were born earlier this month after he edited their embryos using CRISPR technology to remove the CCR5 gene, which plays a critical role in enabling many … Read More
In every semiconductor related field, innovation is the name of the game. Academic, non-profit and government research has been a consistent source of innovation. Look back at the US space program, basic science research and even military programs to see where much of the foundation of our current technological age came from.… Read More
The 21[SUP]st[/SUP] IP-SoC Days conference will be held in Grenoble, France, on December 5-6, 2018. IP-SoC is now the unique IP centric conference, with presentations reflecting the complete IP ecosystem: IP suppliers and foundries, external IP or internal reuse managers. Look at the program, you will see the hot topics covered… Read More
Historically, the semiconductor and semiconductor equipment industry were inextricably linked due to the cyclical nature of the chip industry. An increase in semiconductor revenues was followed within a short period with an increase in equipment revenues, as semiconductor companies purchased equipment to make more chips… Read More
In a recent whitepaper Gagandeep Singh, Director of Engineering at Mentor, a Siemens Business outlines a flow using Catapult Design Checker that helps in early detection of coding errors as many companies are turning to High-Level Synthesis (HLS) methodology. This requires that high -level C++ models are correct, that ambiguities… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival