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Clock Gating Optimization

Clock Gating Optimization
by Bernard Murphy on 09-21-2017 at 7:00 am

You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More


IoT SoCs Demand Good Data Management and Design Collaboration

IoT SoCs Demand Good Data Management and Design Collaboration
by Mitch Heins on 09-20-2017 at 12:00 pm

Design data management has always been important. Board designers have known this for decades as they had to have ways to keep all their discreet components organized and understood. Sourcing components is not easy as it means hours of reading and reviewing specifications, finding reliable sourcing partners and understanding… Read More


Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+

Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+
by Mitch Heins on 09-20-2017 at 12:00 pm

Open Silicon hosted a webinar today focusing on their High Bandwidth Memory (HBM) IP-subsystem product offering. Their IP-subsystem is based on the HBM2 standard and includes blocks for the memory controller, PHY and high-speed I/Os, all targeted to TSMC 16nm FF+ process. The IP-subsystem supports the full HBM2 standard with… Read More


Yield Analysis is a Critical Driver for Profitability

Yield Analysis is a Critical Driver for Profitability
by Daniel Nenni on 09-20-2017 at 7:00 am

One of the most important aspects of any manufacturing effort is the yield of the process. Today, the investment in facilities, equipment and materials is so high that consistently high yields are vital to the profitability of the semiconductor manufacturer. Furthermore, the engineers must get to that consistent high yield … Read More


Improved Memory Design, Characterization and Verification

Improved Memory Design, Characterization and Verification
by Daniel Payne on 09-19-2017 at 12:00 pm

My IC design career started out with DRAM design, characterization and verification back in the 1970’s, so I vividly recall how much SPICE circuit simulation was involved, and how little automation we had back in the day, so we tended to cobble together our own scripts to help automate the process a bit. With each new process… Read More


Partitioning for Prototypes

Partitioning for Prototypes
by Bernard Murphy on 09-19-2017 at 7:00 am

I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software… Read More


What does the Lattice rejection mean for chip M&A?

What does the Lattice rejection mean for chip M&A?
by Robert Maire on 09-18-2017 at 12:00 pm

Although the rejection of the Lattice deal was expected, it none the less has an impact on a number of dynamics in the chip industry and further M&A and consolidation. Freezing out China removes a “catalyst” in the market which help bid up values and add fear to both potential targets or those left out. Cross border… Read More


ATopTech is Back!

ATopTech is Back!
by Daniel Nenni on 09-18-2017 at 7:00 am

One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had… Read More


Burning Man 2017 – My vacation is your worst nightmare

Burning Man 2017 – My vacation is your worst nightmare
by Tom Simon on 09-17-2017 at 5:00 pm

I often use this space to report on industry events I have attended and what I have learned at them. So, this article will be a slight, but not complete, departure from this. I am reporting on my experiences at Burning Man this year. For the unacquainted, Burning Man is a temporary city of around 70,000 people in a remote desert-like … Read More


Webinar: Signoff for Thermal, Reliability and More in Advanced FinFET designs

Webinar: Signoff for Thermal, Reliability and More in Advanced FinFET designs
by Bernard Murphy on 09-17-2017 at 7:00 am

In automotive applications, advanced FinFET processes are great for high levels of integration and low power. But they also present some new challenges in reliability signoff. Ansys will be hosting a webinar to highlight the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge… Read More