See Autonomous Chip Design in Action with ChipAgents at DAC 2026Making the AI wave at DAC 2026 in…Read More
Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026Easy-Logic, a leading provider of high-performance Engineering Change…Read More
The Accidental Infrastructure: How Crypto Miners Built the Foundation of the AI BoomMost crypto forty-niners died broke in a warehouse…Read More
From Detection to Safety: Reframing Fault Simulation for Functional SafetyIn the early 1980s, when computer-aided engineering (CAE),…Read More
Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative MattersThe future of work will not be shaped…Read More
I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement.
At IEDM Applied Materials (AMAT) tried to put together a panel across the entire… Read More
If it’s your job to get a SoC design through synthesis, timing/power closure and final verification, the last thing you need are surprises in new versions of the IP blocks that are integrated into the design. If your IP supplier sends a new version, the best possible scenario is that this is only a small incremental change from… Read More
How Ultra-wideband aligns with 5G’s premise
In part 3, we discussed the time-frequency duality or how time and bandwidth are interchangeable. If one wants to compress in time a wireless transmission, more frequency bandwidth is needed. This property can be used to increase the accuracy of ranging, as we saw in part 3. Another very… Read More
SemiWiki has a new IP partner, PLDA and they bring a lot to the party. Peripheral component interconnect express (PCIe) is a popular high-performance data interface standard. Think GPUs, RAID cards, WiFi cards or solid-state disk (SSD) drives connected to a motherboard. The protocol offers much higher throughput than previous… Read More
Silicon Valley has morphed from the days of semiconductor fabs interspersed between strawberry farms, and 3:00 pm rush-hour traffic during the shift change for the fabrication facility engineers and technicians. The leadership of technology companies has also arguably devolved from people who inspired employees and stewarded… Read More
Security has been a domain blessed with an abundance of methods to improve in various ways, not so much in methods to measure the effectiveness of those improvements. With the best will in the world, absent an agreed security measurement, all those improvement techniques still add up to “trust me, our baby monitor camera is really… Read More
In Part 2, we discussed the second false-start of Ultra-WideBand (UWB) leveraging over-engineered orthogonal frequency-division multiplexing (OFDM) transceivers, launching at the dawn of the great recession and surpassed by a new generation of Wi-Fi transceivers. These circumstances signed the end of the proposed applications… Read More
The old adage, “Time is money”, certainly rings true today for IC designers, so the entire EDA industry has focused on this challenging goal of making tools that help speed up design and physical verification tasks like DRC (Design Rule Checks) and LVS (Layout Versus Schematic). Sure, the big three EDA vendors have… Read More
I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit nanometers). “Design robustness” is a key term – it refers to high quality, high yielding SoCs that come up quickly and reliably in the target system. We all… Read More
Before starting your next FPGA Prototyping Project you should catch the next SemiWiki webinar – “Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards”, in partnership with Aldec.
A significant portion of my 30+ years in the EDA industry has revolved around design verification with some form of FPGA … Read More
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Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?