Taping out a SoC is never easy. The physical dimensions of the chip often belie the work which has been done to get to the tapeout stage. And it is still not a done deal as the hardware and software development teams await the arrival of the test chip from the foundry to complete the post silicon bring-up and validation. The pressure on… Read More
Revolutionizing Hardware Design Debugging with Time Travel TechnologyIn the semiconductor industry High-Level Synthesis (HLS) and…Read More
Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic TestingSilent Data Corruption (SDC) represents a critical challenge…Read More
TSMC's 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability PassionTaiwan Semiconductor Manufacturing Company has once again demonstrated…Read More
Tiling Support in SiFive's AI/ML Software Stack for RISC-V Vector-Matrix ExtensionAt the 2025 RISC-V Summit North America, Min…Read More
TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!Socionext’s recent run of rapid 3D-IC tape-outs is…Read MoreSynopsys Webinar: A Comprehensive Overview of High-Speed Data Center Communications
High-speed communication is a critical component for many applications, most notably in the data center. The serializer/deserializer physical interface, or SerDes PHY is the backbone of many different forms of high-speed communication for this application. Use cases include on chip, between chips, between boards and racks… Read More
VLSI Symposium 2020 – Imec Buried Power Rail
The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Buried Power Rails (BPR) and I had a chance to interview one of the authors, Anshul Gupta.
As logic devices continue to scale down metal pitch is reaching a limit. Imec defines a pitch… Read More
The 10 Worst Cybersecurity Strategies
Counting down to the absolutely worst cybersecurity strategies. Sadly, these are all prevalent in the industry. Many organizations have failed spectacularly simply because they chose to follow a long-term path that leads to disaster. You know who you are…
Let’s count them down.
10. Cyber-Insurance
No need for security, … Read More
Cars and COVID-19 Uncertainty
A funny thing happens when you let car makers make cars and car dealers sell cars – people start buying cars. With the U.S. economy at least partially re-opening nationwide car buyers have returned to the market and, finding a limited supply of new cars and disappointing incentives, have turned, in part, to used cars. This … Read More
How yieldHUB Helps Bring a New Product to Market
Collecting and analyzing semiconductor test data is a subject that holds a special place for me. Developing a factory data collection and analysis system was my first job out of school. The company was RCA, and the factories were in Findlay, Ohio (analog/mixed signal) and West Palm Beach, Florida (digital). There was a pilot… Read More
Thermo-compression bonding for Large Stacked HBM Die
Summary
Thermo-compression bonding is used in heterogeneous 3D packaging technology – this attach method was applied to the assembly of large (12-stack and 16-stack) high bandwidth memory (HBM) die, with significant bandwidth and power improvements over traditional microbump attach.
Introduction
The rapid growth of heterogeneous… Read More
Semiconductors up in 2020? Not so fast
Two months ago most forecasts called for a decline in the semiconductor market in 2020 as reported in our Semiconductor Intelligence May 2020 newsletter. The outlook changed in June, as the Worldwide Semiconductor Trade Statistics (WSTS) consensus forecast projected 3.3% growth in 2020. This month IC Insights revised its IC
Intel 7NM Slip Causes Reassessment of Fab Model
Waving white surrender flag as TSMC dominates-
The quarter was a success but the patient is dying-
Packaging now critical as Moore progress stumbles-
Intel reported a great quarter but weak H2 guidance-
But 7NM slip and “fab lite” talk sends shockwaves-
Intel reported a great quarter beating numbers all around with… Read More
The Polyglot World of Hardware Design and Verification
It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More


Quantum Advantage is About the Algorithm, not the Computer