I Have Seen the Future with ChipAgents Autonomous Root Cause AnalysisI have seen a lot of EDA tool…Read More
Arm FCSA and the Journey to Standardizing Open Chiplet-Based DesignI have written before about an inter-chiplet communication…Read More
Revolution EDA: A New EDA Mindset for a New EraMurat Eskiyerli, PhD, is the founder of Revolution…Read More
WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
In the early stages of the global COVID-19 pandemic, most forecasters expected the semiconductor market to decline in 2020, including our May Semiconductor Intelligence projection of a 6% drop. However, the semiconductor market has shown surprising strength so far this year. WSTS reported the 2Q 2020 semiconductor market … Read More
Did you know you can save 30% to 60% power without spending a fortune on a process migration? There is a better way than moving to deeply scaled nodes for power. Read on…
Have you heard of AGGIOS? You will. The name stands for AGGregated IO Systems, and a team of ex ARM and Qualcomm engineers are re-inventing power management. I’ll explain… Read More
Altair PBS Professional™ is the trusted leader in high-performance computing workload management. It efficiently schedules HPC workloads across all forms of computing infrastructure, and it scales easily to support systems of any size — from clusters to the largest supercomputers.
Scheduling for high-throughput workloads… Read More
In the last article, I wrote about the PCIe basic concepts. This article will reach the physical layer of the PCIe standard.
The lowest PCI Express architectural layer is the Physical Layer. This layer is responsible for actually sending and receiving all the data to be sent across the PCI Express link. The Physical Layer interacts… Read More
This is another post that was requested by a user, and as always i’ll do my best to put in a few articles the basic information that you’ll need to understand how it works at depth level.
PCI Express (or PCIe) is a high-speed serial computer expansion bus designed to replace the older PCI, PCI-X and AGP standards.
The first… Read More
For the 10nm – 5nm nodes, the leading-edge foundries are designing cells which utilize 6 or 7 metal tracks, entailing a wide metal line for every 4 or 5 minimum width lines, respectively (Figure 1).
Figure 1. Left: a 7-track cell. Right: a 6-track cell.
This is a fundamental vulnerability for lithography, as defocus can change… Read More
Similar to my last post on the HCL DevOps webinar series, I will cover their presentation of HCL Compass in a webinar that was recorded on July 29 about how HCL Compass delivers defect tracking and more.
This webinar was presented by Steve Boone, head of product management at HCL Software DevOps, Howie Bernstein, product manager… Read More
The ARC Processor has a rich history. Originally named the Argonaut RISC Processor, it was designed for the Nintendo Game Systems in the 1990s. Argonaut Technologies Limited later became ARC International. My first intimate exposure to ARC was in 2009 when Virage Logic acquired ARC. A year later Virage was acquired by Synopsys… Read More
While Alchip is speeding its way down the TSMC process technology roadmap I am reminded how important services are to the semiconductor ecosystem. We can thank ASIC companies like Alchip for the heavy investment systems companies have made into semiconductors. We covered this in our book “Fabless: The Transformation of the Semiconductor… Read More
You can update ..Generally, I’m a fan of letting market forces figure out best solutions to whatever evolving needs we may have, but I’m enough of a realist to accept that’s not a workable answer to every need. Some problems need a top-down fix. However, we can’t expect policymakers or industry consortia to create compliance demands… Read More
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