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Moving to Deeply Scaled Nodes for Power? There is a Better Way

Moving to Deeply Scaled Nodes for Power? There is a Better Way
by Mike Gianfagna on 08-24-2020 at 10:00 am

Did you know you can save 30% to 60% power without spending a fortune on a process migration? There is a better way than moving to deeply scaled nodes for power. Read on…

AGGIOS DefinitionHave you heard of AGGIOS? You will. The name stands for AGGregated IO Systems, and a team of ex ARM and Qualcomm engineers are re-inventing power management. I’ll explain what AGGIOS is up to in a moment, but first a bit of backstory is in order to set the stage for why AGGIOS technology is so important.  It’s a story of “three P’s”.


For decades, semiconductor companies rode the Moore’s Law curve and migrated to the next process node every two to three years to get the latest boost in performance and reduction in power and area. Lately, that is slowing down quite a bit with a cycle of five to seven years (or more). The price to migrate is skyrocketing and the power benefits are rapidly diminishing.

Deeply Scaled NodesGartner estimates the price tag to design a 7nm SoC to be $270 to over $400 million. This is at least 3x more than the design cost for a 16nm SoC. Costs per chip stay manageable only if end user needs are addressed and the market is large enough to absorb design costs. If you are Apple or Samsung, you have an infrastructure and customer base to accomplish this.

For everyone else these are rare air prices. Gartner estimates that 7nm delivers 65% power reduction over 16nm. A good result, but at a steep price.  For perspective, from 7nm to 5nm the power gain is just 20% – 30%, according to TSMC and Samsung.


A New IdeaPerformance is no longer the leader of the technology adoption curve. For a long time, it was. You could just move to the next process node, increase your clock speed and have a new, competitive product. The flattening of Moore’s and Dennard’s Laws has changed that.

Instead, system design approaches exploit parallelism. Hardware accelerator and multi-core architectures with high-speed communication backbones are leading the way to superior performance. As these technologies significantly stress the power budget, the same need for power reduction exists.


Because of battery life demands, thermal constraints and overall cost to operate data centers, power optimization has become a primary business and technology driver in the semiconductor sector. Even governments are involved with power reduction mandates. All roads lead to reduced power consumption.

Power ManagementA lot of power reduction strategies focus on hardware and process. I’ve touched on process improvements and the associated price tag. Hardware techniques such as clock gating or voltage and frequency scaling can successfully reduce power consumption when closely aligned with software execution. There is an “elephant in the room” problem with all this, however. These methods can deliver good power reduction, but, as with other approaches, it takes a lot of in-house engineering effort, talent and a company-wide vertically integrated hardware/software infrastructure to make it effective. Again, Apple or Samsung has it. For everyone else, it is a challenge.


Effective power management is something everyone needs but only a few can afford. Moving to the next process node is prohibitively expensive and the resultant power reduction is going down in advanced nodes. Performance improvements are being driven by architectural innovations that further stress the power budget. Hardware level approaches can reduce power, but the reductions take a lot of skill, effort and costly infrastructure. If you are moving to deeply scaled nodes for power there is a better way.

A Revolutionary Software-Based Approach to Power Management

A basic truth is that SoCs consume power when they run software. Hardware alone has a hard time understanding the dynamic behavior of the application and system software and its impact on power. What would happen if we enable software to directly optimize every milliwatt? AGGIOS saw the opportunity this presented early-on and developed a patented Software Defined Energy Management system. Their technology delivers fine-grained control of hardware power consumption to the software developer and provides fast and accurate feedback on the impact of software optimizations.

Typical power savings range from 30% to 60% with AGGIOS. So, you can achieve the same or better power reduction associated with expensive process migration and extensive engineering effort without hardware modifications or process migration. At last, what used to be an expensive and labor-intensive but valuable portion of power management is now available to all, not just the special few.  AGGIOS products act exclusively through automated system software and firmware optimization enabling longer lasting, cooler and smaller electronic devices delivered on schedule with much lower cost. Their approach can be applied to any SoC or FPGA architecture.

What would you do with all that power savings? You can read about some real case studies in a white paper from AGGIOS. They document actual results on a series of Xilinx Zynq UltraScale+ MPSoC applications using Xilinx Targeted Reference Designs (TRDs) and other reference applications. The applications include video streaming, video deep learning, ECC processing, memory throughput and two software-defined radios. Their white paper provides a lot of detail on the hardware and software architecture of the applications, how AGGIOS software is applied to the design and the detailed results they achieved.

Speaking of results, the actual power savings reported range from 35% to an eye-popping 86%. Recall that a difficult and expensive move from 16nm to 7nm delivers 65% power savings. The AGGIOS approach is even more effective at deeply scaled nodes as it can account for and even exploit the high variability of these processes to reduce energy consumption or increase performance.

If a new, cost-efficient and highly effective power management strategy sounds appealing, you need to download this white paper. It just may change the direction of your next project, especially if advanced technology migration is being considered or if you’re concerned that gains just won’t be enough. There is a better way than moving to deeply scaled nodes for power. You can download the white paper, titled AGGIOS Seedlings Power Reference Designs: Xilinx UltraScale+ here. 


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