NVIDIA Vera: Rebuilding the CPU for Agentic AISource: Jonathon Evans and Polychronis Xekalakis, “NVIDIA Vera…Read More
High-NA EUV Moves From Experiment to ManufacturingIntel Foundry and ASML say high-numerical-aperture extreme-ultraviolet lithography…Read More
ASML and TSMC’s 12-Inch Photomask Initiative: Technical SignificanceASML and TSMC’s proposed shift from 6-inch to…Read More
When Design Gets Faster, the Bottleneck Moves Through the Physical StackAI can compress the path to tape-out. The…Read More
SEMICON West 2026 arrives at a pivotal moment for the global chip industry. Scheduled for October 13–15 at San Francisco’s Moscone Center, the event returns to the Bay Area after its 2025 edition in Phoenix. Organized by SEMI under the theme “Transform Tomorrow,” it will bring together semiconductor manufacturers, equipment… Read More
Daniel is joined by Dr. Germain Fenger, Senior Director of Product Management at Synopsys where he leads advanced mask solutions and computational lithography technologies. With a background spanning semiconductor manufacturing, lithography research, engineering, and product leadership, Germain has held roles at imec,… Read More
Timothy Regan has substantial experience in analog/ mixed signal design and its supporting EDA technologies. His career began in linear engineering at Texas Instruments.
He then worked as an applications specialist for both GE-Calma and Valid Logic Systems. After that, he spent 10 years as managing director at Design Resources… Read More
While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More
Plessey Semiconductors manufactures monolithic MicroLED displays for near-eye augmented-reality systems, where pixel pitch, brightness, uniformity, and defect density directly determine usable yield. Its process integrates device design, epitaxy, wafer fabrication, bonding, and production in one facility. The displays… Read More
Preamble
Hardware-assisted verification (HAV) platforms, including hardware emulators and FPGA-based prototyping systems, are the two dominant methodologies for validating long workloads on complex System-on-Chip (SoC) designs before tape-out. HAV sits within a broader continuum of verification engines: simulation… Read More
SK hynix’s Hot Chips 2026 presentation explains how High Bandwidth Memory (HBM) is evolving to meet the extraordinary memory requirements of artificial intelligence. Its central message is that future progress will depend not only on better DRAM circuits but also on advanced packaging, denser vertical integration, improved… Read More
Meta recently open-sourced a capable, large-scale agent model — 30 billion parameters, a rough measure of the model’s size and complexity. It’s free, downloadable, and runs, per Meta’s own benchmarks, on a MacBook Pro with an M4 Max or M5 Max chip and 32GB of memory. Their rationale is that powerful agents belong… Read More
Intel Foundry has a blog on LinkedIn that is worth a look. The blogs are by trusted Intel Foundry technical experts and are filled with content. I will cherry pick write a bit about them but be sure and subscribe to this, absolutely.
Intel 18A-P is not a new process node in the conventional sense. It is a performance-enhanced derivative… Read More
SEMI and Silicon Catalyst’s new strategic partnership addresses one of the semiconductor industry’s most persistent technical problems: transforming a promising hardware concept into a manufacturable, commercially viable product. Announced through a memorandum of understanding signed at SEMICON Taiwan 2026, the collaboration… Read More
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ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance