Technical Case Study: MicroLED Yield Management with Plessey and yieldWerxPlessey Semiconductors manufactures monolithic MicroLED displays for near-eye…Read More
Unified Emulation and Prototyping: Pipedream or Reality?Preamble Hardware-assisted verification (HAV) platforms, including hardware emulators…Read More
HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI MemorySK hynix’s Hot Chips 2026 presentation explains how…Read More
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Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First GenerationIntel Foundry has a blog on LinkedIn that is…Read More
There is an interesting article by Kexun ZHang of ChipAgents on their blogsite. This is a company to watch, absolutely. Here is my take on it:
Software engineering has already demonstrated the trajectory of agentic AI. Coding tools progressed from autocomplete to systems that interpret requests, inspect repositories, modify… Read More
AttoTude has expanded its use of Keysight Technologies’ Advanced Design System (ADS) to support an integrated-circuit design flow spanning signaling frequencies from 100 GHz to 3 THz. The company reports that the resulting workflow has reduced IC development cycles by more than 50%, enabling projects to move from concept to… Read More
Agentrys recently launched a new category of design technology, Agentic Design Automation (ADA). The approach promises to revolutionize AI deployment for chip design with technology that facilitates the building of targeted agentic design flows that get better with every run. There is a lot of information available on the … Read More
Intel’s next-generation 14A manufacturing process is showing unusually strong early progress, with defect density falling faster than the company expected. The improvement gives Intel a technical boost as it attempts to restore confidence in its manufacturing operation, win foundry customers and demonstrate that years… Read More
Agentic AI was everywhere at DAC 2026. Various focus areas were presented that covered many parts of the chip design flow. Verification and debug were a popular topic since so much time is spent there. Analog design is another pressure point. Every chip design has analog content. While the size of the analog blocks may not be huge,… Read More
Frontier models (Claude, etc.) are very powerful but becoming expensive for high token counts. Methods to exploit a mix of models, including local open-weight models, are attracting attention. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer… Read More
By Dr. Sabina Kuprėnaitė
Deep-ultraviolet optics used in semiconductor lithography may be exposed to billions of pulses over their service life. That creates a qualification challenge that initial reflectance specifications or laser-induced damage thresholds alone cannot answer.
A mirror may meet its optical specification… Read More
Phillip Stanley-Marbell is the founder and CEO of Signaloid. Up until September 2025, he was a full Professor (Chair of Physical Computation) in the Electrical Engineering Division of the Department of Engineering at the University of Cambridge, where he led the Physical Computation Laboratory. He completed his PhD at Carnegie… Read More
Stephen Strausser was recently appointed CEO of VON ARDENNE North America, Inc. where he will lead the company’s regional strategy, operations, customer engagement and growth initiatives across the US, Canada, Mexico and South America.
Stephen has a powerful blend of business acumen, operations, service/support and engineering… Read More
Daniel is joined by Moshe Tanach, co-founder and CEO of NeuReality. Prior to founding the company, he held senior engineering leadership roles at Marvell and Intel, where he led complex wireless and networking products from architecture through mass production. He also served as AVP of R&D at DesignArt Networks (later acquired… Read More
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The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response