There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?System-on-Chip designs continue to grow in scale and…Read More
Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s EngineeringBy Frank Schirrmeister, Synopsys Disclaimer: This article is…Read More
2026 Outlook with Randy Caplan of Silicon CreationsRandy Caplan is co-founder and CEO of Silicon…Read More
After I published a recent article about Intel, I was contacted by the Irish Development Agency (IDA) where Intel has a large fab presence and asked if I would like to interview them about the Intel site. The interview with Turlough McCormack of the IDA, started with Intel’s presence in Ireland but then went on to paint an interesting… Read More
Dan and Mike are joined by Simon Butler, founder of Methodics and Brad Hart, CTO of Perforce. We explore the acquisition of Methodics by Perforce, including motivation, strategy and a look to the future. We also discuss some of the history of Methodics and how they became successful.
Rich Weber co-founded Semifore in 2006 with Jamsheed Agahi. Rich has a long history of complex chip and system design at companies including Data General, Stardent, Silicon Graphics, StratumOne and Cisco Systems. He received an MS in Electrical Engineering and a BS in Computer Engineering from the University of Illinois, Urbana-Champaign.… Read More
– Business is about as good as it gets- $75B WFE in 2021?
– China remains strong at 32% despite SMIC lack of license
– NAND remains 48% of revs versus 31% foundry
– DRAM steady @ 14% – Service was record $1.3B
Strong results in a strong market
Lam reported revenues of $3.85B and EPS of $7.49 for the March… Read More
It would be nice if there were a pre-packaged set of assertions which could formally check all aspects of cache coherence in an SoC. In fact, formal checks do a very nice job for the control aspects of a coherent network. But that covers only one part of the cache coherence verification task. Dataflow checks are just as important, where… Read More
I haven’t traveled a lot during the COVID-19 pandemic, but I have flown a few times around the U.S. As a former frequent flyer I pride myself on anticipating most travel circumstances and not being surprised or blindsided, but two recent visits to Austin, Texas, changed that when I couldn’t find a rental car.
It was just 12 months … Read More
You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor… Read More
Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance.
ASML a tidal wave of orders
On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir we think memory will lag a bit.… Read More
Agile methods in hardware design are becoming topical again. What does this mean for verification? Paul Cunningham (GM, Verification at Cadence) and I continue our series on research ideas. We’re also honored this month to welcome Raúl Camposano to our blog as a very distinguished replacement for Jim Hogan. As always, feedback… Read More
I read the semiconductor press, LinkedIn and social media (Twitter, Facebook) every morning along with an RSS feed that I setup, staying current on everything related to using EDA tools to make the task of SoC design a bit easier for design teams. A recent press release announced a tool called SoC Compiler, so my curiosity was piqued… Read More
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AI Bubble?