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Semiconductor Expert Forum

Podcast EP54: Ventana Micro, RISC-V, HPC and Chiplets

Podcast EP54: Ventana Micro, RISC-V, HPC and Chiplets
by Daniel Nenni on 12-24-2021 at 10:00 am
Categories: IP, RISC-V
1 Comment

Dan is joined by Balaji Baktha, founder and CEO of Ventana Micro. Balaji explores the application of RISC-V in high-performance applications and the specific advantages of a chiplet-based approach.

RISC-V Summit Panel: https://www.youtube.com/watch?v=duZaAhWxhWM

The views, thoughts, and opinions expressed in these… Read More

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AI for EDA for AI

AI for EDA for AI
by Daniel Nenni on 12-24-2021 at 6:00 am
Categories: Agnisys, AI, EDA

Agnisys AI EDA AI

I’ve been noticing over the last few years that electronic design automation (EDA) vendors just love to talk about artificial intelligence (AI) and machine learning (ML), sometimes with deep learning (DL) and neural networks tossed in as well. It can get a bit confusing since these terms are used in two distinct contexts. The first… Read More

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Scalable Concolic Testing. Innovation in Verification

Scalable Concolic Testing. Innovation in Verification
by Bernard Murphy on 12-23-2021 at 10:00 am
Categories: Cadence, EDA

Scalable Concolic Testing

Combining simulation and symbolic methods is an attractive way to excite rare branches in block-level verification, but is this method really scalable? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always,… Read More

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Cut Out the Cutouts

Cut Out the Cutouts
by Aaron Edwards on 12-23-2021 at 6:00 am
Categories: Ansys, Inc., EDA

ANSYS HFSS 3D Layout 1

In 2014, many of the customers that my team and I supported in North America were still using HFSS 3D to model boards and packages. These customers were content with that interface, able to get their models setup quickly, and were okay with the solution times because when HFSS gave them an answer, they knew it was the right answer. I … Read More

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More Than Moore and Charting the Path Beyond 3nm

More Than Moore and Charting the Path Beyond 3nm
by Kalar Rajendiran on 12-22-2021 at 10:00 am
Categories: Cadence, Chiplet, EDA, Events
1 Comment

Cadence AIML Technologies

The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More

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DAC 2021 – Siemens EDA talks about using the Cloud

DAC 2021 – Siemens EDA talks about using the Cloud
by Daniel Payne on 12-21-2021 at 10:00 am
Categories: EDA, Events, Siemens EDA

Craig Johnson

My third event at DAC on Monday was all about using EDA tools in the Cloud, and so I listened to Craig Johnson, VP EDA Cloud Solutions, Siemens EDA. Early in the day I heard from Joe Sawicki, Siemens EDA, on the topic of Digitalization.

Why even use the Cloud for EDA? That’s a fair question to ask, and Craig had several high-level… Read More

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Topics for Innovation in Verification

Topics for Innovation in Verification
by Bernard Murphy on 12-21-2021 at 6:00 am
Categories: Cadence, EDA

signpost min

Paul, Raúl and I are having fun with our Innovation in Verification series, and you seem to be also, judging by the hit rates we’re getting. We track these carefully to judge what you find most interesting and what seems to fall more under the category of “Meh”. Paul and others also get informal feedback in client meetings but it would… Read More

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DAC 2021 Wrap-up – S2C turns more than a few heads

DAC 2021 Wrap-up – S2C turns more than a few heads
by Ron Green on 12-20-2021 at 10:00 am
Categories: EDA, Emulation, Events, Prototyping, S2C EDA

IMG 7547

Now that the 58th Design Automation Conference held this year in San Francisco has concluded, we take a minute to look back at the results and ascertain what it meant for our company.

Unfortunately, many popular tradeshows held in the time of Covid have suffered a drop in attendance, and DAC was no exception. Despite this however,… Read More

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Bringing PCIe Gen 6 Devices to Market

Bringing PCIe Gen 6 Devices to Market
by Daniel Nenni on 12-20-2021 at 6:00 am
Categories: IP, Truechip

Truechip PCIe Gen 6

PCIe is a prevalent and popular interface standard that is used in just about every digital electronic system. It is used widely in SOCs and in devices that connect to them. Since it was first released in 2003, it has evolved to keep up with rapidly accelerating needs for high speed data transfers. Each version has doubled in throughput,… Read More

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Pattern Shifts Induced by Dipole-Illuminated EUV Masks

Pattern Shifts Induced by Dipole-Illuminated EUV Masks
by Fred Chen on 12-19-2021 at 10:00 am
Categories: Lithography

Pattern Shifts Induced by Dipole Illuminated EUV Masks

As EUV lithography is being targeted towards pitches of 30 nm or less, fundamental differences from conventional DUV lithography become more and more obvious. A big difference is in the mask use. Unlike other photolithography masks, EUV masks are absorber patterns on a reflective multilayer rather than a transparent substrate.… Read More