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Stalling to Uncover Timing Bugs. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification
by Bernard Murphy on 06-29-2022 at 6:00 am

Innovation New

Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More


Intel Foundry Services Puts PDKs in the Cloud

Intel Foundry Services Puts PDKs in the Cloud
by Daniel Nenni on 06-28-2022 at 10:00 am

Intel Foundry Services Roadmap

Intel announced today that they are partnering with cloud and EDA companies to better enable their foundry business. This is a natural extension of the Accelerator ecosystem program announced earlier. More and more chip designs are being done in the cloud and from my experience cloud based designs are better. Some companies use… Read More


Imec Buried Power Rail and Backside Power Delivery at VLSI

Imec Buried Power Rail and Backside Power Delivery at VLSI
by Scotten Jones on 06-28-2022 at 6:00 am

Imec BPR Page 06

At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed … Read More


Time is of the Essence for High-Frequency Traders

Time is of the Essence for High-Frequency Traders
by Dave Bursky on 06-27-2022 at 10:00 am

Figure Simplified block diagram of Multiprotocol PMA from Silicon Creations

In the world of financial trading, nanoseconds count. The faster a trade can be accomplished, the more money a trader can make. Getting a trade in before a competitor also results in improved profits. What does this have to do with the partnership deal recently inked between Silicon Creations and Achronix? Plenty. The two companies… Read More


TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Advanced Packaging Development
by Tom Dillinger on 06-27-2022 at 6:00 am

3D blox

TSMC recently held their annual Technology Symposium in Santa Clara, CA.  The presentations provide a comprehensive overview of their technology status and upcoming roadmap, covering all facets of the process technology and advanced packaging development.  This article will summarize the highlights of the advanced packaging… Read More


Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs
by Daniel Nenni on 06-26-2022 at 6:00 am

Ansys Heat Map

Semiconductor manufacturers are under constantly increasing and intense pressure to accelerate innovative new chip designs to market faster than ever in smaller package sizes while assuring signal integrity and reducing power consumption. Three-dimensional integrated circuits (3D-ICs) promise to answer all these demands… Read More


The Evolution of Taiwan’s Silicon Shield

The Evolution of Taiwan’s Silicon Shield
by Craig Addison on 06-25-2022 at 6:00 am

Silicon Shield 2025 Poster A4 size

The original Silicon Shield theory, as described in my 2001 book, stated that Taiwan’s role as producer of 90 per cent of the world’s IT products (at that time) protected it from an attack by China because the United States, acting in its own self interest, would come to the island’s defense. A similar scenario – involving oil,… Read More


Podcast EP90: A Tour of Cadence’s Cloud Solutions with Mahesh Turaga

Podcast EP90: A Tour of Cadence’s Cloud Solutions with Mahesh Turaga
by Daniel Nenni on 06-24-2022 at 10:00 am

Dan is joined by Mahesh Turaga, VP of Cloud Business Development at Cadence Design Systems. Mahesh brings extensive customer-facing experience to Cadence in business development, strategy, pre-sales, and consulting. He provides an overview of the cloud solutions provided by Cadence. The various business models, technical… Read More


ASML EUV Update at SPIE

ASML EUV Update at SPIE
by Scotten Jones on 06-24-2022 at 6:00 am

12051 4 SPIE2022 Smeets 0.33 NA EUV systems for High Volume Manufacturing Page 07

At the 2022 SPIE Advanced Lithography Conference, ASML presented an update on EUV. I recently had a chance to go over the presentations with Mike Lercel of ASML. The following is a summary of our discussions.

0.33 NA

The 0.33 NA EUV systems are the production workhorse systems for leading edge lithography today. 0.33 NA systems are… Read More


Using STA with Aging Analysis for Robust IC Designs

Using STA with Aging Analysis for Robust IC Designs
by Daniel Payne on 06-23-2022 at 10:00 am

Gate Level Aging min

Our laptops and desktop computers have billions of transistors in their application processor chips, yet I often don’t consider the reliability effects of aging that the transistors experience in the chips. At the recent Synopsys User Group (aka SNUG), there was a technical presentation on this topic from Srinivas Bodapati,… Read More