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Semiconductor Expert Forum

Podcast: Intel’s RISC-V Ecosystem initiative with Junko Yoshida

Podcast: Intel’s RISC-V Ecosystem initiative with Junko Yoshida
by Daniel Nenni on 09-09-2022 at 10:00 am
Categories: Uncategorized

Welcome to our Podcast on Intel’s RISC-V Ecosystem initiative. I’m Junko Yoshida, Editor in Chief‌ of the Ojo-Yoshida Report. Joining me today to discuss the topic are Vijay Krishnan, general manager of RISC-V Ventures at Intel Corp. and Emerson Hsiao, chief operating officer of Andes Technologies USA

The views,… Read More

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CEO Interview: Jan Peter Berns from Hyperstone

CEO Interview: Jan Peter Berns from Hyperstone
by Daniel Nenni on 09-09-2022 at 6:00 am
Categories: CEO Interviews, Hyperstone GmbH, IP
2 Comments

DSCF07001

Since 2012, Dr. Jan Peter Berns is the CEO of Hyperstone, a producer of Flash Memory Controllers for Industrially Embedded Storage Solutions. Before that, he held a Senior Manager Position at Toshiba Electronics for several years. Jan Peter brings more than 20 years of management and executive experience in the semiconductor… Read More

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WEBINAR The Rise of the SmartNIC

WEBINAR The Rise of the SmartNIC
by Don Dingee on 09-08-2022 at 10:00 am
Categories: Achronix, eFPGA, Events

Achronix Webinar - Rise of the SmartNIC

A recent live discussion between experts Scott Schweitzer, Director of SmartNIC Product Planning with Achronix, and Jon Sreekanth, CTO of Accolade Technology, looked at the idea behind the rise of the SmartNIC and ran an “ask us anything” session fielding audience questions about the technology and its use cases.

Three phases

… Read More
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Application-Specific Lithography: 5nm Node Gate Patterning

Application-Specific Lithography: 5nm Node Gate Patterning
by Fred Chen on 09-08-2022 at 6:00 am
Categories: Foundries, Lithography, TSMC
4 Comments

Blur Limitations for EUV Exposure

It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?

Blur Limitations for EUV Exposure

A state-of-the-art

… Read More
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Does SMIC have 7nm and if so, what does it mean

Does SMIC have 7nm and if so, what does it mean
by Scotten Jones on 09-07-2022 at 10:00 am
Categories: Foundries, Semiconductor Services, TechInsights
13 Comments

SMIC 7nm

Recently TechInsights analyzed a Bitcoin Miner chip fabbed at SMIC and declared SMIC has a 7nm process. There has been some debate as to whether the SMIC process is really 7nm and what it means if it is 7nm. I wanted to discuss the case for and against the process being 7nm, and what I think it means.

First off, I want to say I am not going … Read More

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Samtec is Fueling the AI Revolution

Samtec is Fueling the AI Revolution
by Mike Gianfagna on 09-07-2022 at 6:00 am
Categories: AI, Events, Samtec, Semiconductor Services

Samtec is Fueling the AI Revolution

It’s all around us. The pervasive use of AI is changing our world. From planetary analysis of weather patterns to monitoring your vital statistics to assess health, it seems as though smart everything is everywhere. Much has been written about the profound impact AI is having on our lives and society. Everyone seems to agree that… Read More

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Webinar: Semifore Offers Three Perspectives on System Design Challenges

Webinar: Semifore Offers Three Perspectives on System Design Challenges
by Mike Gianfagna on 09-06-2022 at 10:00 am
Categories: EDA, Events, Semifore

Semifore RTL Designer Flow

The exponential increase in design complexity is a popular topic these days. In fact, it’s been a topic of discussion for a very long time. The explosion of chip and system design complexity over the past ten years has become legendary and haunts many of us daily. A lot of the complexity we face has to do with coordinating across an ever-increasing… Read More

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Today’s SoC Design Verification and Validation Require Three Types of Hardware-Assisted Engines

Today’s SoC Design Verification and Validation Require Three Types of Hardware-Assisted Engines
by Daniel Nenni on 09-06-2022 at 6:00 am
Categories: EDA, Siemens EDA

IC Chip Low angle light emitting 600x600

Lauro Rizzatti offers Semiwiki readers a two-part series on why three kinds of hardware-assisted verification engines are now a must have for semiconductor designs continues today. His interview below with Juergen Jaeger, Prototyping Product Strategy Director in the Scalable Verification Solution division at Siemens EDA,… Read More

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Why China hates CHIPS

Why China hates CHIPS
by Craig Addison on 09-05-2022 at 6:00 am
Categories: China, Events
4 Comments

Joe Bidden CHIPS Act 2022

The CHIPS and Science Act has its fair share of critics, with detractors calling it corporate welfare for “losers” like Intel, or lacking guardrails to prevent companies making legacy chips in China.

One of the most vocal opponents of the act has been China’s communist-ruled government.

CHIPS – an acronym for Creating Helpful … Read More

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MAB: The Future of Radio is Here

MAB: The Future of Radio is Here
by Roger C. Lanctot on 09-04-2022 at 6:00 am
Categories: Automotive

MAB The Future of Radio is Here 1

Good story telling is what helps drive change, engage consumers, and define progress. Steve Newberry, CEO of Quu, is a master of the craft.

He told two stories, in particular, at the Michigan Association of Broadcasters event last week in Traverse City, Mich. The first story was to simply note for the broadcasters in attendance

… Read More