Exploring Cycuity’s Radix-ST: Revolutionizing Semiconductor SecurityCycuity’s Radix-ST represents a groundbreaking advancement in semiconductor…Read More
Smart Verification for Complex UCIe Multi-Die ArchitecturesBy Ujjwal Negi - Siemens EDA Multi-die architectures…Read More
PDF Solutions Adds Security and Scalability to Manufacturing and TestEveryone knows design complexity is exploding. What used…Read More
Revolutionizing Processor Design: Intel's Software Defined Super CoresIn the ever-evolving landscape of computing, Intel's patent…Read More
TSMC's 2024 Sustainability Report: Pioneering a Greener Semiconductor FutureTSMC, the world's most trusted semiconductor foundry, released…Read More
The under the radar, sleepy microcontroller market is about to undergo a rapid transformation the next several years with new entrants and the rise of 32 bit cores that will redefine the parameters for success. This will revive growth and result in new winners and losers. But lots of questions remain.
My first job out of college in… Read More
I met with Jeff Wilson, Product Marketing Manager at Mentor in the Calibre product group to learn more about Smart Fill versus Dummy Fill for DFM flows. Jeff works in the Wilsonville, Oregon office and we first meet at Silicon Compilers back in the 1990’s.
Dummy Fill
This diagram shows an IC layout layer on the left as originally… Read More
The Totem webinar will be at 11am on Tuesday 2nd August. This session will be conducted by Karan Sahni, Senior Applications Engineer at Apache Design Solutions. Karan has been with Apache since 2008, supporting the Redhawk, Totem, Sentinel product lines. He received his MS in Electrical Engineering from the Syracuse University… Read More
Hard to believe EDA360, the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat!, is DEAD at the ripe old age of one. As you may have already read John Bruggeman left Cadence after the company conference call last week. The formal announcement should go out on Monday after the SEC… Read More
At DAC Jasper presented a seminar with ARM on cache coherency and verification of cache coherency. The seminar is now available online for those of you that missed DAC or missed the seminar itself.
Cache architectures, especially for multi-core architectures, are getting more and more complex. Techniques originally pioneered… Read More
We have been here before… and when I say “we” I do include myself. Back in 1997, I joined a secretive company called Transmeta. The company was two years old and working on a new x86 microprocessor to challenge Intel. The original focus of the company was not to build a lower power processor, but one that was faster. As with… Read More
Synopsys MIPI Webinar: MIPI is really getting traction
Synopsys last two acquisitions of IP vendors, former ChipIdea in 2009 (Mixed-signal product line of MIPS) and Virage Logic in 2010, have allowed to built a stronger, diversified IP port-folio. Amazingly, Synopsys has found MIPI IP product line in the basket in both cases.… Read More
Competition is what made the semiconductor industry and semiconductors themselves what they are today! Competition is what drives innovation and keeps costs down. Not destructive competition, where the success of one depends on the failure of another, but constructive competition that promotes mutual survival and growth… Read More
Every Semiconductor Analyst has given Intel the once over a hundred times about their slowing PC unit volume. They are looking in the wrong place because the true secret of the Q2 earnings – in my humble opinion – is that Intel’s factories are full and parts are on allocation. What???
Check it out, high-end, 8 and 10 core XEON processors… Read More
The next Apache webinar is on PowerArtist, RTL Power Analysis on July 26th at 11am Pacific time. The webinar will be conducted by David “Woody” Norwood, Principal Applications Engineer at Apache Design Solutions. David has been supporting RTL Power products for the past 8 years. He has broad EDA industry experience… Read More
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MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency