Sr Staff Engineer, Power Integrity (PI), Signoff Lead

About the Role

We are seeking a highly experienced Senior Staff Power Integrity Engineer to serve as the primary technical authority and owner for all IR drop and power delivery aspects of our high-speed CPUs. In this role, you will define sign-off criteria, drive advanced power analysis methodologies, and spearhead the automation of power and IR flows to ensure highly efficient, robust power delivery networks for high-performance compute architectures.

Key Responsibilities

• Technical Leadership: Act as the primary point of contact and subject matter expert for dynamic and static IR signoff criteria across the high-speed CPU design team.
• Power Delivery Architecture: Architect highly efficient, power-density-aware Power Grid (PG) designs and optimize bump maps based on rigorous power density requirements.
• IR Flow Automation: Spearhead the IR drop analysis flow. Collaborate closely with the Physical Design (PD) and Power teams to automate and streamline static and dynamic IR readouts.
• Power Readout Integration: Lead the PrimeTime-PX (PTPX) flow development, partnering with cross-functional teams to seamlessly automate accurate power readouts.

Required Qualifications

• IR Signoff & Tools: Deep, authoritative understanding of dynamic and static IR signoff, including defining pass/fail criteria and margins. Expertise with Ansys tools (e.g., RedHawk) is a must.
• Grid & Bump Design: Deep, hands-on experience with PG grid design and bump placement methodologies driven by complex power density limits.
• Power Analysis: Strong working understanding of PTPX for vector-driven and vectorless power readouts.
• CPU Implementation: Proven experience driving power integrity closure specifically for high-speed CPU architectures.
• Physical Design Flow: Solid foundational understanding of the Physical Design flow, with specific expertise in low power implementation techniques and methodologies.
• Experience: 10+ years of experience in Physical Design with a minimum qualification of bachelor’s or master’s degree.

Preferred Qualifications

• Advanced Packaging: Hands-on experience with 3D IC design and package-silicon co-design is highly preferred.